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HD404374/HD404384/HD404389/ HD404082/HD404084 Series
Low-Voltage AS Microcomputers with On-Chip A/D Converter
REJ03B0050-0500H Rev.5.00 Sep.11.2003
Description
The HD404374, HD404384, and HD404389 Series comprise low-voltage, 4-bit single-chip microcomputers equipped with four 10-bit A/D converter channels, a serial interface, and large-current I/O pins. These devices are suitable for use in applications requiring high resolution A/D converter control, such as battery chargers. The HD404082 and HD404084 series offer less advanced features than the HD404384 series. They are 4bit microcomputers that support low-voltage operation for backward software compatibility. HD404374 Series microcomputers have a 32.768 kHz sub-resonator for realtime clock use, providing a time counting facility, and a variety of low-power modes to reduce current drain. The HD407A4374, HD407A4384, HD407A4389, HD407C4374, HD407C4384, and HD407C4389 are ZTATTM microcomputers with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTAT : Zero Turn-Around Time. ZTAT is a trademark of Renesas Technology Corp.
TM TM
Features
* 20 I/O pins Large-current I/O pins (source: 10 mA max.):4 Large-current I/O pins (sink: 15 mA max.):4 Analog input multiplexed pins: 4 (HD404374, HD404384, and HD404389 Series) * 8-bit timer: 1 channel 16-bit timer: 1 channel (Can also be used as two 8-bit timer channels) * Two timer outputs (including PWM output) * Event counter inputs (edge-programmable) * Clock-synchronous 8-bit serial interface * A/D converter 4 channels x 10-bits (HD404374 and HD404384 Series) 6 channels x 10-bits (HD404389 Series) None (HD404082 and HD404084 Series)
Rev.5.00, Sep.11.2003, page 1 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series * On-chip oscillators HD404374 Series * Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation possible) * Sub-clock (32.768 kHz crystal resonator) HD404384, HD404389, HD404082, and HD404084 Series * Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation possible) Note: * CR oscillation in an optional function. * Interrupts External: 2 (including one edge-programmable) Internal : 5 (HD404374/HD404384/HD404389 Series) : 4 (HD404082/HD404084 Series) * Subroutine stack up to 16 levels, including interrupts * Low-power dissipation modes HD404374 Series: 4 HD404384, HD404389, HD404082, and HD404084 Series: * Module standby (timers, serial interface, A/D converter) * System clock division software switching (1/4 or 1/32) * Inputs for return from stop mode (wakeup): 1 * Instruction execution time Min. 0.89 s (fOSC = 4.5 MHz, division by 1/4) Min. 0.47 s (fOSC = 8.5 MHz, division by 1/4) * Operation voltage 1.8 V to 5.5 V 2.0 V to 5.5 V (ZTAT )
TM
2
Cautions about operation!
* Electrical properties presented on the data sheet for the mask ROM and ZTATTM versions will surely and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin, and other properties may vary depending on differences of manufacturing processes, internal wiring patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an actual system under the same conditions to see its operation. * After power supply has been connected, the values for the memory register, data and stack areas will be undefined. Initialize prior to use.
Rev.5.00, Sep.11.2003, page 2 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Ordering Information
HD404374 Series
ROM (Words) 2,048 RAM (Digits) 512
Type
Product Name Model Name HD404372FT HD404372H HD40A4372 HD40A4372FT HD40A4372H HD40C4372 HD40C4372FT HD40C4372H HD404374 HD40A4374 HD404374FT HD404374H HD40A4374FT HD40A4374H HD40C4374
TM
Package 30-pin plastic SSOP(FP-30D) 48-pin plastic LQFP(FP-48B)
*1
Mask ROM HD404372
30-pin plastic SSOP(FP-30D) 48-pin plastic LQFP(FP-48B) 48-pin plastic LQFP(FP-48B) 4,096
*1
30-pin plastic SSOP(FP-30D)
*1
30-pin plastic SSOP(FP-30D) 48-pin plastic LQFP(FP-48B)
*1
30-pin plastic SSOP(FP-30D) 48-pin plastic LQFP(FP-48B) 48-pin plastic LQFP(FP-48B)
*1
HD40C4374FT HD40C4374H
30-pin plastic SSOP(FP-30D)
*1
ZTAT
HD407A4374 HD407C4374
HD407A4374FT 4,096 HD407C4374FT
30-pin plastic SSOP (FP-30D) 30-pin plastic SSOP(FP-30D)
Rev.5.00, Sep.11.2003, page 3 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404384 Series
ROM (Words) 2,048 RAM (Digits) 512
Type
Product Name Model Name HD404382FT HD404382S HD404382H HD40A4382 HD40A4382FT HD40A4382S HD40A4382H HD40C4382 HD40C4382FT HD40C4382S HD40C4382H HD404384 HD404384FT HD404384S HD404384H HD40A4384 HD40A4384FT HD40A4384S HD40A4384H HD40C4384 HD40C4384FT HD40C4384S HD40C4384H
TM
Package 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B)
*1 *1
Mask ROM HD404382
30-pin plastic SSOP (FP-30D)
30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) 4,096 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B)
*1 *1
30-pin plastic SSOP (FP-30D)
30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B)
*1 *1
30-pin plastic SSOP (FP-30D)
ZTAT
HD407A4384
HD407A4384FT 4,096 HD407A4384S
30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S)
HD407C4384
HD407C4384FT HD407C4384S
Rev.5.00, Sep.11.2003, page 4 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 Series
Type Product Name Model Name HD404388FT HD40A4388FT HD40C4388FT HD404389FT HD40A4389FT HD40C4389FT HD407A4389FT 16,384 HD407C4389FT 16,384 ROM (Words) 8,192 RAM (Digits) 512 Package 30-pin plastic SSOP (FP-30D)
Mask ROM HD404388 HD40A4388 HD40C4388 HD404389 HD40A4389 HD40C4389 ZTAT
TM
HD407A4389 HD407C4389
Rev.5.00, Sep.11.2003, page 5 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404082 Series
ROM (Words) 1,024 RAM (Digits) 128
Type
Product Name Model Name HD404081FT HD404081S HD404081H HD40A4081 HD40A4081FT HD40A4081S HD40A4081H HD40C4081 HD40C4081FT HD40C4081S HD40C4081H HD404082 HD404082FT HD404082S HD404082H HCD404082 HD40A4082 HCD404082 HD40A4082FT HD40A4082S HD40A4082H HD40C4082 HD40C4082FT HD40C4082S HD40C4082H HCD40C4082 HCD40C4082
TM
Package 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B)
*2 *2
Mask ROM HD404081
30-pin plastic SSOP (FP-30D)
30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) 2,048 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) chip 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B)
*2 *2 *2
30-pin plastic SSOP (FP-30D)
30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 48-pin plastic LQFP (FP-48B) chip
*2
ZTAT
TM
Uses HD404384 series ZTAT .
Notes: 1. The FP-48B is subject to the following limitations: TM (1) It is available in a mask ROM version only. For debugging, etc., the ZTAT version of a different package will need to be used. (2) The WS version will become available at the beginning of mass production. 2. Currently in planning stage.
Rev.5.00, Sep.11.2003, page 6 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404084 Series
Type Product Name Model Name HD404084FT HD404084S HCD404084 HD40A4084 HCD404084 HD40A4084FT HD40A4084S HD40C4084 HD40C4084FT HD40C4084S HCD40C4084 ZTAT
TM
ROM (Words) 4,096
RAM (Digits) 256
Package 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) chip 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) 30-pin plastic SSOP (FP-30D) 28-pin plastic DILP (DP-28S) chip
Mask ROM HD404084
HCD40C4084
TM
Uses HD404384 series ZTAT
Rev.5.00, Sep.11.2003, page 7 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
List of Functions
HD404374, HD40A4374, HD40C4374, HD407A4374, HD407C4374 4,096 ZTAT PROM HD404384, HD40A4384, HD40C4384, HD407A4384, HD407C4384 4,096 ZTAT PROM
Product Name ROM(words) RAM (digit) I/O Large-current I/O pins
HD404372, HD40A4372, HD40C4372 2,048 512 20 (max)
HD404382, HD40A4382, HD40C4382 2,048
HD404388, HD40A4388, HD40C4388 8,192
4 (source, 10 mA max), 4 (sink, 15 mA max)
Analog input 4 multiplexed pins Timer/ counter Timer output Event input Serial interface A/D converter Interrupt sources Low-power modes Stop mode Watch mode Standby mode External Internal 3 2 (PWM output possible) 1 (edge selection possible) 1 (8-bit synchronous) 10 bits x 4 channels 2 5 4 Available Available Available -- -- 2 10 bits x 6 channels
Subactive mode Available Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation CR oscillation Available Available Available Available
Available (HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082, HD40C4084, HCD40C4084) Available (32.768kHz) --
Sub-oscillator
Crystal oscillation
Rev.5.00, Sep.11.2003, page 8 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404374, HD40A4374, HD40C4374, HD407A4374, HD407C4374 HD404384, HD40A4384, HD40C4384, HD404388, HD407A4384, HD40A4388, HD407C4384 HD40C4388
Product Name Minimum instruction execution time
HD404372, HD40A4372, HD40C4372
HD404382, HD40A4382, HD40C4382
0.47 ms (fOSC = 8.5 MHz) : HD40A4372, HD40A4374, HD407A4374, HD40A4382, HD40A4384, HD407A4384, HD40A4388, HD40A4389, HD407A4389, HD40A4081, HD40A4082, HD40A4084 0.89 ms (fOSC = 4.5 MHz) : HD404372, HD404374, HD404382, HD404384, HD404388, HD404389, HD404081, HD404082, HCD404082, HD404084, HCD404084 1.14 ms (fOSC = 3.5 MHz) : HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082, HD40C4084, HCD40C4084
Operating voltage (V) Package FP-30D DP-28S FP-48B Chip Guaranteed operation temperature(C)
1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTATTM Available -- Available -- -20 to +75: Mask ROM -40 to +85: ZTATTM Available -- --
Rev.5.00, Sep.11.2003, page 9 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404389, HD40A4389, HD40C4389, HD404081, HD40C4081 HD404082, HD40A4082, HD40C4082 HCD404082, HCD40C4082 HD404084, HD40A4084, HD40C4084 HCD404084, HCD40C4084 HD407A4389, HD40A4081,
Product Name ROM(words) RAM (digit) I/O Large-current I/O pins
HD407C4389
16,384 1,024 ZTAT PROM 512 20 (max) 128
2,048
4,096
4 (source, 10 mA max), 4 (sink, 15 mA max) --
Analog input 4 multiplexed pins Timer/ counter Timer output Event input Serial interface A/D converter Interrupt sources Low-power modes Stop mode Watch mode Standby mode External Internal 3
2 (PWM output possible) 1 (edge selection possible) 1 (8-bit synchronous) 10 bits x 6 channels 2 5 4 Available Available Available 4 --
Subactive mode Available Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation CR oscillation Available Available Available Available Available (HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082, HD40C4084, HCD40C4084) --
Sub-oscillator
Crystal oscillation
Rev.5.00, Sep.11.2003, page 10 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404389, HD40A4389, HD40C4389, HD404081, HD40C4081 HD404082, HD40A4082, HD40C4082 HCD40482, HCD40C4082 HD404084, HD40A4084, HD40C4084 HCD404084, HCD40C4084 HD407A4389, HD40A4081,
Product Name Minimum instruction execution time
HD407C4389
0.47 s (fOSC = 8.5 MHz) : HD40A4372, HD40A4374, HD407A4374, HD40A4382, HD40A4384, HD407A4384, HD40A4388, HD40A4389, HD407A4389, HD40A4081, HD40A4082, HD40A4084 0.89 s (fOSC = 4.5 MHz) : HD404372, HD404374, HD404382, HD404384, HD404388, HD404389, HD404081, HD404082, HCD404082, HD404084, HCD404084 1.14 s (fOSC = 3.5 MHz) : HD40C4372, HD40C4374, HD407C4374, HD40C4382, HD40C4384, HD407C4384, HD40C4388, HD40C4389, HD407C4389, HD40C4081, HD40C4082, HCD40C4082, HD40C4084, HCD40C4084
Operating voltage (V) Package FP-30D DP-28S FP-48B Chip Guaranteed operation temperature(C)
1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTATTM Available -- -- -- -20 to +75: Mask ROM -40 to +85: ZTATTM Available In planning stage -- -- Available +75 -- -20 to +75: Mask ROM -40 to +85: ZTATTM Available +75 Available --
Rev.5.00, Sep.11.2003, page 11 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Pin Arrangement
HD404374 Series
GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVss OSC1 OCS2 TEST X2 X1 R00/
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FP-30D (Top View)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/ 0 R22/SI/SO R21/ R20/TOC R13/TOB R10/EVNB
AVCC VCC NC GND NC D9 NC NC D8 D7 NC D6
N-MOS large current pins R70/AN0 R71/AN1 R72/AN2 R73/AN3 NC AVSS OSC1 NC OSC2 NC TEST X2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 FP-48B 31 6 (Top View) 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
NC
0
D5 D4 NC D3 NC D2 NC P-MOS large current pins D1 NC D0/ 0 NC R22/SI/SO
Rev.5.00, Sep.11.2003, page 12 of 161
NC R10/EVNB NC R13/TOB NC R20/TOC R21/
X1 NC
R00/
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404384 Series
GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVss OSC1 OCS2 TEST NC NC R00/
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14
FP-30D (Top View)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 28 27 26 25 24 23 22 21 20 19 18 17 16 15
D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/ 0 R22/SI/SO R21/ R20/TOC R13/TOB R10/EVNB
GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVss OSC1 OCS2 TEST R00/ 0 R10/EVNB
DP-28S (Top View)
D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/ 0 R22/SI/SO R21/ R20/TOC R13/TOB
AVCC VCC NC GND NC D9 NC NC D8 D7 NC D6
N-MOS large current pins R70/AN0 R71/AN1 R72/AN2 R73/AN3 NC AVSS OSC1 NC OSC2 NC TEST NC 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 FP-48B 30 7 (Top View) 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 D5 D4 NC D3 NC D2 NC N-MOS large current pins D1 NC D0/ 0 NC R22/SI/SO
NC NC
NC
0
Rev.5.00, Sep.11.2003, page 13 of 161
NC R10/EVNB NC R13/TOB NC R20/TOC R21/
R00/
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404389 Series
GND Vcc AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 AN4 AN5 AVSS TEST OSC1 OSC2 R00/
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FP-30D (Top View)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/ 0 R22/SI/SO R21/ R20/TOC R13/TOB R10/EVNB
HD404082 and HD404084 Series
GND VCC NC R70 R71 R72 R73 NC OSC1 OSC2 TEST NC NC R00/
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FP-30D (Top View)
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/ 0 R22/SI/SO R21/ R20/TOC R13/TOB R10/EVNB
N-MOS large current pins
P-MOS large current pins
GND VCC NC R70 R71 R72 R73 NC OSC1 OSC2 TEST R00/ 0 R10/EVNB
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DP-28S (Top View)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/ 0 R22/SI/SO R21/ R20/TOC R13/TOB
N-MOS large current pins
P-MOS large current pins
Rev.5.00, Sep.11.2003, page 14 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Pad Arrangement
HCD404082 and HCD404084
26
25
24
23
3
2
1
22
Model Name
4
21
5 6
20 19 7 18 8 17 9 16
10
11
12
13
14
15
Model Name: HD404082 (HCD404082) HD404084 (HCD404084)
Rev.5.00, Sep.11.2003, page 15 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Pad Coordinates
HCD404082 and HCD404084
Y Chip size (X x Y): Coordinates: Home point position: Pad size (X x Y): Chip thickness: 4.63 x 4.77 (mm) Pad center Chip center 90 x 90 (m) 280 (m)
Mold
X Chip center (X=0,Y=0)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Pad name GND VCC R70 R71 R72 R73 OSC1 OSC2 TEST RESETN R00 R10 R13 X (m) -458 -826 -1338 -1338 -1338 -1338 -1338 -1338 -1338 -1197 -577 -194 189
Coodinates Y (m) 1403 1403 1403 1006 525 285 -550 -954 -1251 -1403 -1403 -1403 -1403
Pad No. 14 15 16 17 18 19 20 21 22 23 24 25 26 Pad name R20 R21 R22 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 X (m) 572 982 1338 1338 1338 1338 1338 1338 1338 1153 751 349 -53
Coodinates Y (m) -1403 -1403 -1403 -1020 -637 -254 129 768 1170 1403 1403 1403 1403
Rev.5.00, Sep.11.2003, page 16 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Pin Description
HD404374 and HD404384 Series
Pin Number Item Power supply Test Reset Symbol VCC GND TEST RESET FP-30D DP-28S*2 2 1 11 14 9 2 1 11 12 9 DP-48B 47 45 11 15 7 I/O -- -- Input Input Input Function Apply the power supply voltage to this pin. Connect to ground. Not for use by the user application. Connect to GND potential. Used to reset the MCU. Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. When using CR oscillation, connect a resistor. Realtime clock oscillator input/output pins. Connect a 32.768 kHz crystal. If 32.768 kHz crystal oscillation is not used, fix the X1 pin to VCC and leave the X2 pin open. I/O pins addressed bit by bit. D0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). I/O pins, addressed in 4-bit units.
Oscillation OSC1 OSC2 X1
10 13*1 12*1 21-30
10 --
9 13*1 12*1
Output Input
X2 Port D0-D9
-- 19-28
Output
27, 29, 31, 33, 35- I/O 37, 39, 40, 43
R00, R10, R13, R20, R21, R22, R70-R73 Interrupt Wakeup Serial interface Timer A/D converter INT0 WU0 SCK SI SO TOB,TOC EVNB AVCC AVSS AN0-AN3 Other NC
15-20, 4-7 21 15 19 20 20 17, 18 16 3
13-18, 4-7 19 13 17 18 18 15, 16 14 3
17, 19, 21, 23-25, I/O 1-4 27 17 24 25 25 21, 23 19 48 Input Input I/O Input Output Output Input --
External interrupt input pin Input pin used for transition from stop mode to active mode. Serial interface clock I/O pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pins Event count input pin A/D converter power supply pin. Connect as close as possible to the VCC pin so as to be at the same potential as VCC. Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. A/D converter analog input pins Connect to GND potential.
8
8
6
--
4-7 12*2, 13*2
4-7 --
1-4
Input
5, 8, 10, 12*2, -- 13*2, 14, 16, 18, 20, 22, 26, 28, 30, 32, 34, 38, 41, 42, 44, 46
Notes: *1 Applies to HD404374 Series. *2 Applies to HD404384 Series.
Rev.5.00, Sep.11.2003, page 17 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 Series
Pin Number Item Power supply Test Reset Symbol VCC GND TEST RESET FP-30D 2 1 11 14 12 13 21-30 I/O -- -- Input Input Input Output I/O Function Apply the power supply voltage to this pin. Connect to ground. Not for use by the user application. Connect to GND potential. Used to reset the MCU. Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. When using CR oscillation, connect a resistor. I/O pins addressed bit by bit. D0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). I/O pins, addressed in 4-bit units.
Oscillation OSC1 OSC2 Port D0-D9
R00, R10, R13, R20, R21, R22, R70-R73 Interrupt Wakeup Serial interface INT0 WU0 SCK SI SO Timer TOB,TOC EVNB A/D converter AVCC AVSS AN0-AN5
15-20, 4-7 21 15 19 20 20 17, 18 16 3 10 4-9
I/O
Input Input I/O Input Output Output Input -- -- Input
External interrupt input pin Input pin used for transition from stop mode to active mode. Serial interface clock I/O pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pins Event count input pin A/D converter power supply pin. Connect as close as possible to the VCC pin so as to be at the same potential as VCC. Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. A/D converter analog input pins
Rev.5.00, Sep.11.2003, page 18 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404082 and HD404084 Series
Pin Number Item Power supply Test Reset Symbol VCC GND TEST RESET FP-30D DP-28S Chip 2 1 11 14 9 10 21-30 2 1 11 12 9 10 19-28 2 1 9 10 7 8 17-26 I/O -- -- Input Input Input Function Apply the power supply voltage to this pin. Connect to ground. Not for use by the user application. Connect to GND potential. Used to reset the MCU. Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit.
Oscillation OSC1 OSC2 Port D0-D9
Output When using CR oscillation, connect a resistor. I/O I/O pins addressed bit by bit. D0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). I/O pins, addressed in 4-bit units.
R00, R10, R13, R20, R21, R22, R70-R73 Interrupt Wakeup Serial interface INT0 WU0 SCK SI SO Timer TOB,TOC EVNB Other NC
15-20, 4-7 21 15 19 20 20 17, 18 16
13-18, 4-7 19 13 17 18 18 15, 16 14
11-16, 3-6 17 11 15 16 16 13, 14 12 --
I/O
Input Input I/O Input
External interrupt input pin Input pin used for transition from stop mode to active mode. Serial interface clock I/O pin Serial interface receive data input pin
Output Serial interface transmit data output pin Output Timer output pins Input -- Event count input pin Connect to GND potential.
3, 8, 12, 3, 8 13
Rev.5.00, Sep.11.2003, page 19 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Block Diagram
HD404374 and HD404384 Series
TEST OSC1 OSC2 X1 * X2 * Vcc GND
HMCS400 CPU
D Port
ROM
RAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
P-MOS large current buffer
N-MOS large current buffer
0 0
R0 Port
External interrupt control circuit
R00
R1 Port
8-bit timer A TOB 8-bit timer B EVNB
R10 R13 R20 R21 R22 R70 R71 R72 R73
TOC
8-bit timer C
SI/SO AVcc AN0 AN1 AN2 AN3 AVss
8-bit synchronous serial interface
A/D converter 10 bit x 4 channels
: Data bus Note : * Applies to HD404374 Series.
R7 Port
R2 Port
: Signal line
Rev.5.00, Sep.11.2003, page 20 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404389 Series
TEST OSC1 OSC2 Vcc GND
HMCS400 CPU
D Port
ROM
RAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
P-MOS large current buffer
N-MOS large current buffer
0 0
R0 Port
External interrupt control circuit
R00
R1 Port
8-bit timer A TOB 8-bit timer B EVNB
R10 R13 R20 R21 R22 R70 R71 R72 R73
TOC
8-bit timer C
SI/SO AVcc AN0 AN1 AN2 AN3 AN4 AN5 AVss
8-bit synchronous serial interface
A/D converter 10 bit x 6 channels
: Data bus
R7 Port
R2 Port
: Signal line
Rev.5.00, Sep.11.2003, page 21 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404082 and HD404084 Series
TEST OSC1 OSC2 Vcc GND
HMCS400 CPU
D Port
ROM
RAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
P-MOS large current buffer
N-MOS large current buffer
0 0
R0 Port
External interrupt control circuit
R00
R1 Port
8-bit timer A TOB 8-bit timer B EVNB
R10 R13 R20 R21 R22 R70 R71 R72 R73
TOC
8-bit timer C
SI/SO
8-bit synchronous serial interface
: Data bus
R7 Port
R2 Port
: Signal line
Rev.5.00, Sep.11.2003, page 22 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Memory Map
ROM Memory Map The ROM memory map is shown in figure 1 and is described below. Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the program is executed from the vector address. A JMPL instruction should be used to branch to the start address of the reset routine or the interrupt routine. Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to $003F with the CAL instruction. Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data with the P instruction. Program area ($0000 to $03FF (HD404081, HD40A4081, HD40C4081)), ($0000 to $07FF (HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382, HD404082, HCD404082, HD40A4082, HD40C4082, HCD40C4082)), ($0000 to $0FFF (HD404374, HD40A4374, HD40C4374, HD404384, HD40A4384, HD40C4384, HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD404084, HCD404084, HD40A4084, HD40C4084, HCD40C4084)), ($0000 to $1FFF (HD404388, HD40A4388, HD40C4388)), ($0000 to $3FFF (HD404389, HD40A4389, HD40C4389, HD407A4389, HD407C4389)).
Rev.5.00, Sep.11.2003, page 23 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
ROM address $0000 $000F $0010 Vector addresses (16 words) Zero page subroutine area (64 words) $003F $0040 $03FF $0400 Pattern and program area (1,024 words) *1 Pattern and program area (2,048 words) *2 $07FF $0800 ROM address $0000 $0001 $0002 $0003 $0004 $0005 JMPL instruction (Jump to reset routine) JMPL instruction (Jump to 0 routine) JMPL instruction (Jump to 0 routine)
$0008 $0009 $000A $000B $000C
JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B routine) JMPL instruction (Jump to timer C routine) JMPL instruction (Jump to A/D or serial interface routine)
Pattern and program area (4,096 words) *3
$000D $000E $000F
$0FFF $1000 Pattern and program area (8,192 words) *4
Notes: *1 HD404081, HD40A4081, HD40C4081 *2 HD40372, HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382, HD404082, HCD404082, HD40A4082, HD40C4082, HCD40C4082 *3 HD404374, HD40A4374, HD40C4374, HD404384, HD40A4384, HD40C4384, HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD404084, HCD404084, HD40A4084, HD40C4084, HCD40C4084 *4 HD404388, HD40A4388, HD40C4388 *5 HD404389, HD40A4389, HD40C4389, HD407A4389, HD407C4389
$1FFF $2000
Pattern and program area (16,384 words) *5
$3FFF
Figure 1 ROM Memory Map RAM Memory Map The MCU has on-chip RAM comprising a memory register area, data area, and stack area. In addition to these areas, an interrupt control bit area, special register area, and register flag area are mapped onto RAM memory space as a RAM-mapped register area.The RAM memory map is shown in figure 2 and described below. After power supply has been connected, regardless of a reset, the values for the memory register, data and stack areas will be undefined. Make sure to initialize prior to use.
Rev.5.00, Sep.11.2003, page 24 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
HD404374 Series HD404384 Series HD404389 Series
$000 $000
HD404082 Series
$000
HD404084 Series
$000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Interrupt control bit area Speed Select Reg. Miscellaneous Reg. Not used Port Mode Reg.0 Port Mode Reg.1 Port Mode Reg.2 Port Mode Reg.3 (PMR0) (PMR1) (PMR2) (PMR3) W W W W W W W W W R/W R/W W W R/W R/W (SSR) (MIS) W W
RAM-mapped register area
RAM-mapped register area
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area (16 digits)
$03F $040 $04F $050
Memory register (MR) area (16 digits)
$03F $040 $04F $050
Memory register (MR) area (16 digits)
Not used
Not used
Not used
$08F $090
$08F $090 Data (48 digits) $0BF $0C0
$08F $090
Not used Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Not used
*1
*1
Data (176 digits)
$01F $020 Data (432 digits) $13F $140 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C Not used $02F $030 $031 $032 $033 $034 $035 $036 $037 Port D0~D3 DCR Port D4~D7 DCR Port D8~D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Not used $03A $03B $03C Port R7 DCR Not used $03F $3FF $3FF $3FF (DCR7) W (DCR0) (DCR1) (DCR2) W W W Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper A/D Mode reg. A/D Data Reg.Lower A/D Data Reg.Middle A/D Data Reg.Upper Not used (DCD0) (DCD1) (DCD2) W W W (SMR1) W (SMR2) W (SRL) R/W (SRU) R/W (AMR) W (ADRL) R (ADRM) R (ADRU) R
Not used $23F $240
*2 *2 *2 *2
Not used
$3BF $3C0
$3BF $3C0
$3BF $3C0
Stack area (64 digits)
Stack area (64 digits)
Stack area (64 digits)
Notes: R W
: Read : Write
$012 $013 $016 $017
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper
(TRBL) (TRBU) (TRCL) (TRCU)
R R R R
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper
(TWBL) W (TWBU) W (TWCL) W (TWCU) W
R/W : Read/Write
*1 Two registers are mapped onto
the same address ($012, $013, $016, $017).
*2 Applies to HD404374, HD404384, and HD404389 Series.
Figure 2 RAM Memory Map
Rev.5.00, Sep.11.2003, page 25 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series RAM-mapped register area ($000 to $03F): * Interrupt control bit area ($000 to $003) This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. * Special register area ($004 to $01F, $024 to $03F) This area comprises mode registers and data registers for external interrupts, the serial interface, timers, A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and 5. These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used on the other registers. * Register flag area ($020 to $023) This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. Memory register (MR) area ($040 to $04F): In this data area, the 16 memory register digits (MR(0) to MR(15)) can also be accessed by the registerregister instructions LAMR and XMRA. The configuration of this area is shown in figure 6. Data area ($090 to $23F (HD404374, HD404384, HD404389 Series)) ($090 to $0BF (HD404082 Series)) ($090 to $13F (HD404084 Series)) Stack area ($3C0 to $3FF): This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved data and saved status information are shown in figure 6. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by the RTN instruction. Any part of the area not used for saving can be used as a data area.
Rev.5.00, Sep.11.2003, page 26 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
RAM address $000 (
0
Bit 3 IMWU interrupt mask)
Bit 2 IFWU ( 0 interrupt request flag) Not used IFTB (Timer B interrupt request flag) IFAD *2 (A/D converter interrupt request flag)
Bit 1 RSP (Stack pointer reset) IM0 interrupt mask) IMTA (Timer A interrupt mask) IMTC (Timer C interrupt mask) (
0
Bit 0 IE (Interrupt enable flag) IF0 interrupt request flag) IFTA (Timer A interrupt request flag) IFTC (Timer C interrupt request flag) (
0
$001
Not used IMTB (Timer B interrupt mask) IMAD *2 (A/D converter interrupt mask)
$002
$003
$020
DTON *1 (DTON flag) GEF (Gear enable flag)
ADSF *2 (A/D start flag) Not used
WDON (Watchdog on flag) Not used
LSON *1 (Low speed on flag) Not used
$021
$022
Not used IMS (Serial interrupt mask)
Not used IFS (Serial interrupt request flag)
Not used
Not used
$023
Not used
Not used
IF IM IE SP Notes: *1 Applies to HD404374 Series. *2 Applies to HD404374, HD404384, and HD404389 Series.
: Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer
Figure 3 Interrupt Control Bit and Register Flag Area Configuration
Rev.5.00, Sep.11.2003, page 27 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. SEM/SEMD IE IM LSON *1 IF ICSF ICEF GEF RSP WDON ADSF
*2
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed
Allowed Allowed Allowed Not executed Inhibited Allowed Not executed
Allowed Inhibited Inhibited Inhibited Allowed Allowed Inhibited
DTON *1 Not Used
Notes : The WDON bit is reset only by stop mode clearance by means of an MCU reset. Do not use the REM or REMD instruction on the ADSF bit during A/D conversion. The DTON bit is always in the reset state in active mode. If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent bit, the status flag value will be undetermined * 1 Applies to HD404374 Series. * 2 Applies to HD404374, HD404384, and HD404389 Series.
Figure 4 Instruction Restrictions
Rev.5.00, Sep.11.2003, page 28 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
RAM address $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Bit 3 Bit 2 Bit 1 Bit 0
Interrupt control bit area
*1 32 kHz frequency division*1 32 kHz oscillation stop setting ratio selection
System clock selection *1 System clock frequency division ratio switching
SSR MIS
Pull-up MOS control
Not used
Interrupt frame period selection *1
Not used Not used 0 D0/ Not used R00/ 0 Not used R13/TOB R10/EVNB R20/TOC R22/SI/SO R21/ Not used Timer B lock on/off Timer C clock on/off Not used Serial clock on/off A/D clock on/off *2 Not used Timer A / time base Timer A clock source selection Reload on/off Timer B clock source selection Timer B output mode setting EVNB edge detection selection Not used Timer B register (lower) Timer B register (upper) Timer C clock source selection Reload on/off Time C output mode selection Not used Not used Timer C register (lower) Timer C register (upper)
PMR0 PMR1 PMR2 PMR3 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU
Not used $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C
Register flag area Serial transfer clock speed selection Not used Not used SO idle H/L setting Serial data register (lower) Serial data register (upper) Analog channel selection *2 A/D conversion time *2 A/D data register (bit 1, 0) *2 Not used A/D data register (bit 5 to 2) *2 A/D data register (bit 9 to 6) *2
R22/SI/SO PMOS control
SMR1 SMR2 SRL SRU AMR ADRL ADRM ADRU
Not used $02F DCD0 $030 DCD1 $031 DCD2 $032 $033 DCR0 $034 DCR1 $035 DCR2 $036 $037 PortD3DCR PortD2DCR PortD1DCR PortD6DCR PorD5DCR PortD7DCR Not used PortD9DCR Not used Not used Not used PortR13DCR Not used PortR22DCR PortR21DCR Not used $03A DCR7 $03B $03C PortR73DCR PortR72DCR PortR71DCR PortR70DCR PortD0DCR PortD4DCR PortD8DCR PortR00DCR PortR10DCR PortR20DCR
Not used $03F Notes: *1 Applies to HD404374 Series. *2 Applies to HD404374, HD404384, and HD404389 Series.
Figure 5 Special Function Register Area
Rev.5.00, Sep.11.2003, page 29 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
$040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR (0) MR (1) MR (2) MR (3) MR (4) MR (5) MR (6) MR (7) MR (8) MR (9) MR (10) MR (11) MR (12) MR (13) MR (14) MR (15) 960 Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level 1,023 Level 16 $3C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 $3FF
Bit 3 1020 1021 1022 1023 ST
10
Bit 2
13
Bit 1
12
Bit 0
11
$3FC $3FD $3FE $3FF
9
8
7
CA
3
6
5
4
2
1
0
(a) Memory registers
(b) Stack area PC13 to PC0 ST CA : Program counter : Status flag : Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Rev.5.00, Sep.11.2003, page 30 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations. they are shown in figure 7 and described below.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) (SPX) (Y) (X) (W) (A)
0
0
0
0
0
0
0
Carry flag
Initial value: Undefined, R/W
0 (CA) 0 (ST) 0 (PC)
Status flag Program counter Initial value: $0000, no R/W Stack pointer Initial value: $3FF, no R/W
Initial value: 1, no R/W 13
9 1 1 1 1
5 (SP)
0
Figure 7 Registers and Flags Accumulator (A) and B register (B): The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data transfer to or from memory, an I/O area, or another register.
Rev.5.00, Sep.11.2003, page 31 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series W register (W), X register (X) and Y register (Y): The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register indirect addressing. The Y register is also used for D port addressing. SPX register (SPX) and SPY register (SPY): The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers, respectively. Carry flag (CA): This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Status flag (ST): This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic, compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Program counter (PC): This is a 14-bit binary counter that holds ROM address information. Stack pointer (SP): The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at 1111, so that a maximum of 16 stack levels can be used. There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above, or by resetting the RSP bit with the REM or REMD instruction. Reset An MCU reset is performed by driving the RESET pin low. At power-on, and when subactive mode, watch mode, or stop mode is cleared, RESET should be input for at least tRC to provide the oscillation settling time for the oscillator.In other cases, the MCU is reset by inputting RESET for at least two instruction cycles. Table 1 shows the areas initialized by an MCU reset, and their initial values.
Rev.5.00, Sep.11.2003, page 32 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 1 (1) Initial Values after MCU Reset
Item Program counter Status flag Stack pointer Interrupt Interrupt enable flag Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0 ~ 2) (DCR00 , DCR10, DCR13, DCR20 - DCR22, DCR70 - DCR73) (PMR0) (PMR1) (PMR2) (PMR3) (TMA) (TMB1) (TMB2) (TMC1) (TMC2) (PSS) (PSW) (TCA) (TCB) (TCC) (TWBU,L) (TWCU,L) Initial value $0000 1 $3FF 0 0 1 Contents Program executed from ROM start address Branching by conditional branch instruction enabled Stack level is 0 All interrupts disabled No interrupt requests Interrupt requests masked
flags/ mask Interrupt request flag Interrupt mask I/O Port data register Data control registers Data control registers
All bits 1 "1" level output possible All bits 0 Output buffer off (high impedance) All bits 0
Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Timers Timer mode register A Timer mode register B1 Timer mode register B2 Timer mode register C1 Timer mode register C2 Prescaler S Prescaler W Timer/counter A Timer/counter B Timer/counter C Timer write register B Timer write register C
---0 ---0 0--0 0000 0000 0000 -000 0000 -0-$000 $00 $00 $00 $00 $X0 $X0
See port mode register 0 section See port mode register 1 section See port mode register 2 section See port mode register 3 section See timer mode register A section See timer mode register B1 section See timer mode register B2 section See timer mode register C1 section See timer mode register C2 section
Rev.5.00, Sep.11.2003, page 33 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 1 (2) Initial Values after MCU Reset
Item Serial interface Serial mode register 1 Serial mode register 2 Serial data register Octal counter A/D converter A/D mode register A/D data register U A/D data register M A/D data register L Bit registers Low speed on flag Watchdog timer on flag A/D start flag Direct transfer on flag Gear enable flag Others Miscellaneous register System clock select register (AMR) (ADRU) (ADRM) (ADRL) (LSON) (WDON) (ADSF) (DTON) (GEF) (MIS) (SSR) Abbr. (SMR1) (SMR2) (SRU,L) Initial value 0000 -0X$XX 000 0000 0111 1111 11- 0 0 0 0 0 0-00 0000 --00 --00 See low-power mode section See timer C section See A/D converter section See low-power mode section See system clock gear function See low-power mode and input/output sections See low-power mode and oscillator circuit sections See timer section See serial interface and A/D converter sections See A/D mode register section See A/D data register section Contents See serial mode register 1 section See serial mode register 2 section
Module standby register 1 (MSR1) Module standby register 2 (MSR2)
Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in table 1 (3). 2. X: Indicates invalid value, - indicates that the bit does not exist.
Table 1 (3) Initial Values after MCU Reset
Item Carry flag Accumulator B register W register Abbr. (CA) (A) (B) (W) After Stop Mode Clearance by WU0 Retain value immediately prior to entering stop mode After Other MCU Reset Value immediately prior to MCU reset is not guaranteed. Must be initialized by program.
X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM
Rev.5.00, Sep.11.2003, page 34 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Interrupts There are a total of seven interrupt sources, comprising wakeup input (WU0), external interrupts (INT0), timer/counter (timer A, timer B, timer C) interrupts, a serial interface interrupt, and an A/D converter interrupt. Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control interrupts as a whole. Of the interrupt sources, the A/D converter and serial interface share the same vector address. Software must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt handling. Interrupt control bits and interrupt handling: The interrupt control bits are mapped onto RAM addresses $000 to $003 and $023, and can be accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are initialized to 0, and the interrupt masks (IM) are initialized to 1. Figure 8 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The vector address corresponding to the interrupt source is generated by the priority control circuit. The interrupt handling sequence is shown in figure 9, and the interrupt handling flowchart in figure 10. When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the vector address and instruction execution is resumed from that address. In each vector address area, a JMPL instruction should be written that branches to the start address of the interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be reset by software. Table 2 Vector Addresses and Interrupt Priorities
Priority -- 1 2 3 4 5 6 Vector Address $0000 $0002 $0004 $0008 $000A $000C $000E
Interrupt Source RESET WU0 INT0 Timer A Timer B Timer C Serial interface, A/D converter
Rev.5.00, Sep.11.2003, page 35 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
$000,0
I/E Interrupt request
$000,2
(
0 interrupt)
IFWU
$000,3
IMWU Priority control circuit Vector address
$001,0
(
0 interrupt)
IF0
$001,1
IM0
$002,0
(Timer A interrupt) IFTA
$002,1
IMTA
$002,2
(Timer B interrupt) IFTB
$002,3
IMTB
$003,0
(Timer C interrupt) IFTC
$003,1
IMTC
$003,2
(A/D interrupt) IFAD
$023,2
IFS (Serial interrupt)
$003,3
IMAD
$023,3
IMS
Figure 8 Block Diagram of Interrupt Control Circuit
Rev.5.00, Sep.11.2003, page 36 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 3 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Control Bit IE IFWU*IMWU IF0*IM0 IFTA*IMTA IFTB*IMTB IFTC*IMTC IFAD*IMAD+IFS*IMS WU0 1 1 * * * * * INT0 1 0 1 * * * * Timer A 1 0 0 1 * * * Timer B 1 0 0 0 1 * * Timer C 1 0 0 0 0 1 * A/D or Serial 1 0 0 0 0 0 1
Note: * Operation is not affected whether the value is 0 or 1.
Instruction cycle 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Save to stack IE reset
Save to stack Vector address generated
Execution of JMPL instruction at vector address
Execution of instruction at start address of interrupt routine
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.
Figure 9 Interrupt Sequence
Rev.5.00, Sep.11.2003, page 37 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Power ON
="0"?
No
Yes Interrupt request? No
Yes
IE="1"? Yes Accept interrupt
Execute instruction Reset MCU
PC(PC)+1
IE"0" Stack(PC) Stack(CA) Stack(ST)
PC$0002
Yes
0
interrupt? No PC$0004 Yes
0
interrupt? No Yes
PC$0008
Timer A interrupt?
No PC$000A Yes Timer B interrupt? No PC$000C Yes Timer C interrupt?
No PC$000E (A/D, serial interrupt)
Figure 10 Interrupt Handling Flowchart
Rev.5.00, Sep.11.2003, page 38 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Interrupt enable flag (IE: $000,0): The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4. The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction. Table 4 Interrupt Enable Flag (IE: $000,0)
Interrupt Enabling/Disabling Interrupts disabled Interrupts enabled
Interrupt Enable Flag (IE) 0 1
Wakeup interrupt request flag (IFWU: $000,2): The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in WU0 input in active mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected at the wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. When a transition is made from stop mode to active mode with IE set to 1 and IMWU cleared to 0, wakeup interrupt handling is executed after the switch to active mode. The wakeup interrupt request flag (IFWU) is not set in this case (table 5). Table 5 Wakeup Interrupt Request Flag (IFWU: $000,2)
Interrupt Request No wakeup interrupt request Wakeup interrupt request generated
Wakeup Interrupt Request Flag (IFWU) 0 1
Wakeup Interrupt Mask (IMWU: $000,3): his bit masks an interrupt request by the wakeup interrupt request flag (table 6). Table 6 Wakeup Interrupt Request Mask (IMWU: $000,3)
Interrupt Request Wakeup interrupt request enabled Wakeup interrupt request masked (held pending)
Wakeup Interrupt Mask (IMWU) 0 1
External interrupt request flag (IF0: $001, 0): The external interrupt request flag is set by an INT0 input falling edge (table 7). Table 7 External Interrupt Request Flag (IF0: $001, 0)
Interrupt Request No external interrupt request External interrupt request generated
External Interrupt Request Flag (IF0) 0 1
Rev.5.00, Sep.11.2003, page 39 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series External interrupt mask (IM0: $001, 1): This bit masks an interrupt request by the external interrupt request flag (table 8). Table 8 External Interrupt Mask (IM0: $001, 1)
Interrupt Request External interrupt request enabled External interrupt request masked (held pending)
External Interrupt Mask (IM0) 0 1
Timer A interrupt request flag (IFTA: $002,0): The timer A interrupt request flag is set by timer A overflow output (table 9). Table 9 Timer A Interrupt Request Flag (IFTA: $002,0)
Interrupt Request No timer A interrupt request Timer A interrupt request generated
Timer A Interrupt Request Flag (IFTA) 0 1
Timer A interrupt mask (IMTA: $002,1): This bit masks an interrupt request by the timer A interrupt request flag (table 10). Table 10 Timer A Interrupt Mask (IMTA: $002,1)
Interrupt Request Timer A interrupt request enabled Timer A interrupt request masked (held pending)
Timer A Interrupt Mask (IMTA) 0 1
Timer B interrupt request flag (IFTB: $002,2): The timer B interrupt request flag is set by timer B overflow output (table 11). Table 11 Timer B Interrupt Request Flag (IFTB: $002,2)
Interrupt Request No timer B interrupt request Timer B interrupt request generated
Timer B Interrupt Request Flag (IFTB) 0 1
Rev.5.00, Sep.11.2003, page 40 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer B interrupt mask (IMTB: $002,3): This bit masks an interrupt request by the timer B interrupt request flag (table 12). Table 12 Timer B Interrupt Mask (IMTB: $002,3)
Interrupt Request Timer B interrupt request enabled Timer B interrupt request masked (held pending)
Timer B Interrupt Mask (IMTB) 0 1
Timer C interrupt request flag (IFTC: $003,0): The timer C interrupt request flag is set by timer C overflow output (table 13). Table 13 Timer C Interrupt Request Flag (IFTC: $003,0)
Interrupt Request No timer C interrupt request Timer C interrupt request generated (held pending)
Timer C Interrupt Request Flag (IFTC) 0 1
Timer C interrupt mask (IMTC: $003,1): This bit masks an interrupt request by the timer C interrupt request flag (table 14). Table 14 Timer C Interrupt Mask (IMTC: $003,1)
Interrupt Request Timer C interrupt request enabled Timer C interrupt request masked (held pending)
Timer C Interrupt Mask (IMTC) 0 1
Serial interrupt request flag (IFS: $023,2): The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted midway (table 15). Table 15 Serial Interrupt Request Flag (IFS: $023,2)
Serial Interrupt Request Flag (IFS) Interrupt Request 0 1 No serial interrupt request Serial interrupt request generated
Rev.5.00, Sep.11.2003, page 41 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial interrupt mask (IMS: $023,3): This bit masks an interrupt request by the serial interrupt request flag (table 16). Table 16 Serial Interrupt Mask (IMS: $023,3)
Interrupt Request Serial interrupt request enabled Serial interrupt request masked (held pending)
Serial Interrupt Mask (IMS) 0 1
A/D interrupt request flag (IFAD: $003,2) (Applies to HD404374, HD404384, and HD404389 Series): The A/D interrupt request flag is set on completion of A/D conversion (table 17). Table 17 A/D Interrupt Request Flag (IFAD: $003,2)
A/D Interrupt Request Flag (IFAD) Interrupt Request 0 1 No A/D interrupt request A/D interrupt request generated
A/D interrupt mask (IMAD: $003,3) (Applies to HD404374, HD404384, and HD404389 Series): This bit masks an interrupt request by the A/D interrupt request flag (table 18). Table 18 A/D Interrupt Mask (IMAD: $003,3)
Interrupt Request A/D interrupt request enabled A/D interrupt request masked (held pending)
Serial Interrupt Mask (IMAD) 0 1
Rev.5.00, Sep.11.2003, page 42 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Operating Modes The five operating modes shown in table 19 can be used for the MCU. The function of each mode is shown in table 20, and the state transition diagram among each mode in figure 11. Table 19 Operating Modes and Clock Status
Mode Name Active Activation method Standby Stop STOP instruction when TMA3 = 0 Watch*
1
Subactive* *
1,
3
SBY RESET cancellation, instruction interrupt request, WU0 input in stop mode STOP/SBY instruction in subactive mode (when direct transfer is selected) OP
1
STOP instruction when TMA3 = 1
INT0/timer A or WU0 interrupt request in watch mode
Status
System oscillator
OP OP RESET input, interrupt request
Stopped OP*
2
Stopped OP
Stopped OP
Subsystem oscillator* OP Cancellation method RESET input, STOP/SBY instruction
RESET input, WU0 input
RESET input, RESET STOP/SBY input, INT0/timer A instruction or WU0 interrupt request
Notes: OP: implies in operation. 1. Applies to HD404374 Series. 2. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $004) 3. Subactive mode is an optional function; specify it on the fnction option list.
Rev.5.00, Sep.11.2003, page 43 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 20
Function CPU RAM Timer A Timer B Timer C Serial interface A/D * I/O
4
Operation in Low-Power Dissipation Modes
Stop Mode Retained Retained Stopped Stopped Stopped Stopped * Stopped Retained
2
Watch mode* Retained Retained OP Stopped Stopped Stopped * Stopped Retained
2
1
Standby Mode Retained Retained OP OP OP OP OP Retained
Subactive Mode* * OP OP OP OP OP OP Stopped OP
1,
3
Notes: OP: implies in operation. 1. Applies to HD404374 Series. 2. Transmission/Reception is activated if a clock is input in external clock mode. However, interrupts stop. 3. Subactive mode is an optional function specified on the function option list. 4. Applies to HD404374, HD404384, and HD404389 Series.
Rev.5.00, Sep.11.2003, page 44 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Reset by pin input or watchdog timer
Stop mode (TMA3=0,SSR3=0,LSON=0) fosc fx
CPU CLK
Reset
0
PER
: Stop : Active : Stop : Stop : Stop
Standby mode fosc fx
CPU CLK PER
Active mode SBY instruction (TMA3=0,SSR3=1,LSON=0) STOP instruction fosc : Stop fx : Stop 0 CPU : Stop CLK : Stop STOP PER : Stop *5 instruction *4 SBY instruction (TMA3=1) fosc fx
CPU CLK
: Active : Active : Stop : fcyc : fcyc
fosc fx
CPU CLK
interrupt
PER
: Active : Active : fcyc : fcyc : fcyc (TMA3=0)
Subactive mode fosc fx
CPU CLK PER
fosc fx
CPU CLK PER
: Active : Active : Stop : fw : fcyc
interrupt
PER
: Active : Active : fcyc : fw : fcyc
*1
: Stop : Active : fSUB : fw : fSUB
STOP instruction *2 Timer A, 0 or 0 interrupt Watch mode fosc fx fosc : fx : fcyc : fw : fSUB : CPU : CLK : PER : LSON : DTON : TMA3 : Main oscillator frequency Sub-oscillator frequency (for realtime clock) fOSC/32 or fOSC/4 (selected by software) fx/8 fx/8 or fx/4 (selected by software) System clock Clock for realtime clock Peripheral function clock Low speed on flag Direct transfer on flag Timer mode register A bit3
CPU CLK PER
STOP instruction
*3
Timer A, 0 or 0 interrupt
: Stop : Active : Stop : fw : Stop
fosc fx
CPU CLK PER
: Stop : Active : Stop : fw : Stop
(TMA3=1,LSON=0) Transition Condition *1 *2 *3 *4 STOP/SBY instruction STOP/SBY instruction STOP/SBY instruction STOP/SBY instruction
(TMA3=1,LSON=1) DTON 1 0 Don't care 0 LSON 0 0 1 0 TMA3 1 1 1 0
*5 Applies to HD404384, HD404389, HD404082, and HD404084 Series. Note: Watch mode and subactive mode apply to HD404374 Series.
Figure 11 MCU Status Transitions
Rev.5.00, Sep.11.2003, page 45 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Active mode: In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC1 and OSC2 oscillator circuits. Standby mode: In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral functions continue to operate. Power consumption is lower than in active mode due to the halting of the CPU. The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is cleared by RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode and executes a instruction following the SBY instruction. After executing the instruction, if the interrupt enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt request is held pending and normal instruction execution is continued. MCU operation flowchart is shown in figure 12.
Rev.5.00, Sep.11.2003, page 46 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Stop mode Standby mode Watch mode*1
=0? No =0? Yes Yes
No
IFWU* =1? Yes IF0* Yes
No
No
0
= Yes
?
= 1?
No
IFTA * = 1? Yes
No
IFTB * = 1? Yes*2 System clock oscillator started
No
IFTC* = 1? Yes*2
No
System reset
IFAD* IFS* Yes*2
+ = 1?
No
System clock oscillator started
NOP
Next Instruction execution
System clock oscillator started
Notes: 1. Applies to HD404374 Series 2. Only when clearing from standby mode
No
IF = 1, IM = 0, IE = 1? Yes
Next Instruction execution
Interrupts enabled
Figure 12 MCU Operation Flowchart
Rev.5.00, Sep.11.2003, page 47 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Stop mode: In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This mode thus has the lowest power consumption of all operating mode. In stop mode, the OSC1 and OSC2 oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR: $004) (figure 22) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators. The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode register A (TMA: $00F) (figure 33) is cleared to 0 in active mode. Stop mode is cleared by RESET or WU0 input. When stop mode is cleared by RESET, the RESET signal should be input for at least the oscillation settling time (tRC) (see "AC Characteristics") shown in figure 13. Then, the MCU is initialized and starts instruction execution from the start (address 0) of the program (IE = 0, IMWU = 0). If IE is set before entering stop mode (IE = 1, IMWU = 0), wakeup interrupt handling is executed after the transition to active mode. When the MCU detects a falling edge at WU0 in stop mode, it automatically waits for the oscillation settling time, then switches to active mode. After the transition to active mode, the MCU resumes program execution from the instruction following the STOP instruction. If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop mode.
Stop mode Oscillator
Internal clock
tres STOP instruction executed (At least oscillation settling time (tRC))
Figure 13 Timing Chart for Clearing Stop Mode by RESET Input Note: If stop mode is cleared by wakeup input when an external clock is used as the system clock (OSC1), the subclock should not be stopped in stop mode. Watch mode ( Applies to HD404374 Series) : In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators operate, but other functions stop. This mode thus has the second lowest power consumption after stop mode, and is useful for performing realtime clock display only. In watch mode, the OSC1 and OSC2 oscillators stop but the X1 and X2 oscillators continue to operate. The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction in subactive mode.
Rev.5.00, Sep.11.2003, page 48 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Watch mode is cleared by RESET input or an INT0,timer A or WU0 interrupt request. For RESET input, refer to the section on stop mode. When watch mode is cleared by an INT0, timer A or WU0 interrupt request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if LSON = 0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt request generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the timer A interrupt, and, for the INT0 interrupt or WU0 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1 and 0 (MIS1, MIS0) of the miscellaneous register are set to 00, or Tx (tRC < Tx < T + tRC) if MIS1 and MIS0 are set to 01 or 10 (figures 14 and 15). Other operations when the transition is made are the same as when watch mode is cleared (figure 12). Subactive mode ( Applies to HD404374 Series): In subactive mode, the OSC1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. A CPU instruction processing speed of 244 s or 122 s can be selected according to whether bit 2 (SSR2) of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should be changed (01 or 10) only in active mode. If the value is changed in subactive mode, the MCU may operate incorrectly. Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct transfer on flag (DTON: $020,3). Subactive mode is a function option, and should be specified in the function option list. Interrupt frame ( Applies to HD404374 Series): In watch mode and subactive mode, oCLK is supplied to the timer A, WU0, and INT0 acceptance circuits. Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two values can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005) (figure 15). In watch mode and subactive mode, the timing for generation of timer A, INT0 and WU0 interrupts is synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt strobe timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at the interrupt strobe timing.
Rev.5.00, Sep.11.2003, page 49 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe
0, 0
Interrupt request generation T Only in case of transition to active mode T TX T: Interrupt frame period tRC : Oscillation stabilization period tRC
Note: If the time from the fall of the 0 or 0 signal until the interrupt is accepted and active mode is entered and is designated TX, then TX will be in the following range : T+tRC TX 2T+tRC (MIS1, MIS0=00) tRC TX T+tRC (MIS1, MIS0=01 or 10)
Figure 14 Interrupt Frame
Miscellaneous Register (MIS: $005) Bit Read/Write Reset Bit name 3 W 0 MIS3 Not 2 W 0 used*4 1 W 0 MIS1*1 0 W 0 MIS0*1
See pull-up MOS control, figure 30
MIS1 0 1
MIS0 0 1 0 1
Interrupt Frame Oscillation Settling period T(ms)*2 Time tRC(ms)*2 0.24414 3.90625 3.90625
Oscillator Circuit Condition
0.12207(0.24414)*3 External clock input, CR oscillation frequency 7.8125 Ceramic resonator 31.25 Crystal resonator Not used
Notes: *1. Applies to HD404374 series. *2. T and tRC values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins. *3. This value applies only in case of direct transition operation. *4. Must always be cleared to 0. Setting to 1 will cause incorrect operation.
Figure 15 Miscellaneous Register (MIS)
Rev.5.00, Sep.11.2003, page 50 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Direct transition from subactive to active mode (Applies to HD404374 Series): A direct transition can be made from subactive mode to active mode by controlling the direct transfer on flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below. (a) Set LSON = 0 and DTON = 1 in subactive mode. (b) Execute a STOP or SBY instruction. (c) After the lapse of the MCU internal processing time and the oscillation settling time, the MCU automatically switches from subactive mode to active mode (figure 16). Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in active mode. 2. The condition for transition time TD from the subactive mode to active mode is as follows: tRC < TD < T + tRC.
STOP/SBY instruction execution Subactive mode (Set LSON =0, DTON =1) MCU internal processing time Oscillation stabilization time Active mode
Interrupt strobe
Direct transition completion timing T TD tRC T: Interrupt frame period tRC: Oscillation settling time TD: Direct transition time
Figure 16 Direct Transition Timing MCU operation sequence: The MCU operates in accordance with the flowchart shown in figure 17. RESET input is asynchronous input, and the MCU immediately enters the reset state upon RESET input, regardless of its current state. In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.
Rev.5.00, Sep.11.2003, page 51 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
STOP/SBY instruction
IF=1 IM=0 Yes
No
Standby/watch mode (HD404374 Series) No
Stop Mode
IE=0 Yes No
Interrupt handling routine
IF=1 IM=0 Yes
0
No
= Yes
Clearing Standby watch mode Hardware NOP Execution Hardware NOP Execution
Clearing Stop mode
NOP
PC (PC)+1 PC (PC)+1 PC (PC)+2
Instruction Execution
Instruction Execution
MCU Operation Cycle
Note: See figure 12, MCU Operation Flowchart, for IF and IM operation.
Figure 17 MCU Operating Sequence (Low-Power Mode Operation)
Rev.5.00, Sep.11.2003, page 52 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Usage notes (Applies to HD404374 Series): In watch mode and subactive mode, an interrupt will not be detected correctly if the INT0 or WU0 high or low-level period is shorter than the interrupt frame period. The MCU's edge sensing method is shown in figure 18. The MCU samples the INT0 and WU0 signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a falling edge has been generated. Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the highlevel period of the INT0 or WU0 signal is within an interrupt frame, as shown in figure 19 (a), the signal will be low at point A and point B, with the result that the falling edge will not be recognized. Similarly, If the low-level period of the INT0 or WU0 signal is within an interrupt frame, as shown in figure 19 (b), the signal will be high at point A and point B, with the result that the falling edge will not be recognized. In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the INT0 and WU0 signals is at least as long as the interrupt frame period.
0
or
0
Sampling High Low Low
Figure 18 Edge Sensing Method
(a) High-level mode
(b) Low-level mode
0
or
0
0
or
0
Interrupt frame
Point A: Low
Point B: Low
Interrupt frame
Point A: High
Point B: High
Figure 19 Sampling Examples
Rev.5.00, Sep.11.2003, page 53 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Internal Oscillator Circuit
Figure 20 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1 and X2. External clock operation is possible for the system oscillator. CR oscillation for system oscillator is possible. CR oscillation function is optional. Set bit 1 (SSR1) of the system clock select register (SSR: $004) according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 22). Note: If the setting of bit 1 in the system clock select register does not match the frequency of the system oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly in the HD404374 Series. Also, the CR oscillation frequency differs depending on the operating voltage and resistance value. Set bit 1 of the system clock select register to match the operating frequency. Note that if the frequency being used does not match the setting of bit 1 of the system clock select register, subsystems using the 32.768 kHz oscillation frequency will not operate correctly.
LSON OSC2 System oscillator fOSC 1/4 or 1/32 fcyc Timing tcyc generation division circuit* circuit System clock selection circuit
CPU
CPU * ROM * RAM * Registers, flags * I/O
OSC1
PER
X2 Sub system clock oscillator X1 Time base clock selection circuit fx 1/8 or 1/4 fSUB Timing division tsubcyc generator circuit* circuit
Peripheral functions Interrupts
TMA3 bit
CLK
1/8 division circuit HD404374 series
Timing fW generation twcyc circuit
Timer A interrupts
Notes: * The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register (SSR:$004).
Figure 20 Clock Pulse Generator Circuit
Rev.5.00, Sep.11.2003, page 54 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
System Clock Gear Function
The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be selected by software for the instruction execution time. Efficient power consumption can be achieved by operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at the other times. Figure 21 shows the system clock conversion method. System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction. When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is entered. In this case a transition is made to standby mode for the duration of the gear conversion, but after the synchronization time has elapsed, a transition is made automatically to active mode. As soon as the transition is made to active mode, the gear enable flag is reset. The same procedure is used for conversion from division-by-32 to division-by-4. Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may result if an interrupt is generated during gear conversion.
Division-by-32 setting (SSR0 = 1)
Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction
Division-by-4 setting (SSR0 = 0) Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction
Figure 21 System Clock Division Ratio Conversion Flowchart
Rev.5.00, Sep.11.2003, page 55 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Make sure to set bit 3 of the system clock select register to 1 if the HD404374 series is being used without the subsystem clock, and on the HD404384, HD404389, HD404082, and HD404084 series. The microcomputer will malfunction if the setting is not 1. System clock select register (SSR: $004) Bit Read/Write Initial value on reset Bit name 3 W 0 SSR3 2 W 0 SSR2* 1 W 0 SSR1* 0 W 0 SSR0
System clock division ratio switch 0 1 Division-by-4 (fcyc - fOSC/4) Division-by-32 (fcyc - fOSC/32)
System clock division ratio switch 0 1 fosc=0.4-1.0MHz fosc=1.6-8.5MHz
Subsystem clock division ratio switch 0 1 Subsystem clock stop setting (HD404374 Series) 0 1 Subsystem clock operates in stop mode Subsystem clock stops in stop mode fSUB=fx/8 fSUB=fx/4
This bit must be set to 1 following power-on and reset if the HD404374 series is being used without the subsystem clock, and on the HD404384, HD404389, HD404082, and HD404084 series. If it is set to 0 (the initial value), malfunctioning may occur in the stop mode. Note: * Applies to HD404374 Series. The CR oscillation frequency differs depending on the operating voltage and resistance value. Set SSR1 to match the operating frequency. Note that if the frequency being used does not match the SSR1 setting, subsystems using the 32.768 kHz oscillation frequency will not operate correctly.
Figure 22 System Clock Select Register
Rev.5.00, Sep.11.2003, page 56 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 21 Oscillator Circuit Examples
Circuit Structure External clock operation
External oscillator Open
Circuit Constants
OSC1
OSC2
Ceramic oscillator (OSC1, OSC2)
C1 OSC1
Ceramic oscillator
Ceramic oscillator: CSA4.00MG (Murata)
Rf GND C2 C1
OSC2
Rf=1M20% C1=C2=24pF20%
Crystal oscillator (OSC1, OSC2)
OSC1 Crystal oscillator Rf GND C2
OSC1 Rf OSC2
Rf=1M20% C1=C2=10-20pF20%
OSC2
CR oscillator* (OSC1, OSC2)
4
Rf=20k1%
Crystal oscillator (X1, X2) HD404374 Series
C1 X1 Crystal oscillator X2 GND C2
Crystal: 32.768 kHz: MX38T (Nihon Denpa Kogyo) C1=C2=20pF20%
Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray capacitance in the interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. 2. Make the connections between the OSC1 and OSC2 pins (X1 and X2 pins) and external components as short as possible, and ensure that no other lines cross these lines (see layout example in figure 23). 3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at VCC and leave the X2 pin open. 4. Applies to HD40C4372, HD40C4374, HD40C4382, HD40C4384, HD40C4388, HD40C4389, HD40C4081, HD40C4082, HCD40C4082, HD40C4084, HCD40C4084, HD407C4374 and HD407C4384.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
AVSS
AVSS
OSC1
OSC1
OSC2
OSC2
TEST
TEST
X2
NC
X1
NC (GND)
RESET (GND) HD404374 Series
RESET
HD404384/HD404389/HD404082/HD404084 Series
Figure 23 Typical Layouts of Crystal and Ceramic Oscillator
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Input/Output
The MCU has 20 input/output pins (D0 to D9, R0, R10, R13, R20 to R22, R70 to R73). The features of these pins are described below. * The four pins D0 to D3 are source large-current (10 mA max.) I/O pins. * The four pins D4 to D7 are sink large-current (15 mA max.) I/O pins. * I/O pins comprise pins (D0, R00, R10, R13, R20 to R22, R70 to R73) that also have a peripheral function (timer, serial interface, etc.). With these pins, the peripheral function setting has priority over the D port or R port pin setting. When a peripheral function setting has been made for a pin, the pin function and input/output mode will be switched automatically in accordance with that setting. * Selection of input or output for I/O pins, or selection of the port or peripheral function for pins multiplexed as peripheral function pins, is performed by the program. * All output of the peripheral function pins are CMOS outputs. The SO pin and R22 port pin can be designated as NMOS open-drain output by the program. * A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also reset, input/output pins go to the high-impedance state. * Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program. Figure 24 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by the program. Table 23 shows the circuit configuration of each I/O pin.
VCC Pull-up control signal Pull-up MOS VCC PMOS Buffer control signal DCD, DCR MIS3
Output data NMOS Input data Input control signal
PDR
Figure 24 I/O Pin Circuit Configuration
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 22 Programmable I/O Circuits
0 0 0 PMOS NMOS Pull-up MOS Note: -- : OFF -- -- -- 1 -- -- -- 0 -- ON -- 1 1 ON -- -- 0 -- -- -- 0 1 -- -- ON 0 -- ON -- 1 1 1 ON -- ON
MIS3 (bit 3 of MIS) DCD,DCR PDR CMOS buffer
Table 23 Circuit Configurations of I/O Pins
Type I/O pins Circuit Configuration
VCC VCC Pull-up control signal Buffer control signal Output data PDR Input data Input control signal VCC VCC Pull-up control signal Buffer control signal Output data MIS3 DCR SMR22 PDR MIS3 DCD, DCR
Pins D0-D9 R00 R10, R13 R20, R21
R22 *2 R70-R73
Input data Input control signal
VCC
Pull-up control signal VCC Buffer control signal Output data
MIS3 DCR PDR
R70-R73 *1 AN0-AN3
A/D input A/D channel control signal Input data Input control signal
Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404374, HD404384, and HD404389 Series. 2. Applies to HD404082 and HD404084 Series.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 23
Type Perip- I/O pins heral function pins
Circuit Configurations of I/O Pins (cont)
Circuit Configuration
VCC VCC Pull-up control signal MIS3 PDR I/O control signal
Pins SCK
Output data
Input data
SCK
Output pins
VCC
VCC
Pull-up control signal PMOS control signal Output data
SO
MIS3 PDR SMR22 SO
VCC
VCC
Pull-up control signal
TOB, TOC
MIS3 PDR TOB, TOC
Output data
Input pins
Input data
RESET
RESET
VCC MIS3 PDR
WU0, INT0, EVNB, SI
0
etc.
AN4, AN5
A/D Input A/D channel control signal
*1
Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404389 Series.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series D Port The D port consists of 10 I/O pins that are addressed bit-by-bit. Ports D0 to D3 are source large-current I/O pins, and ports D4 to D7 are sink large-current I/O pins. The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions. Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD or TDD instruction. The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to $032). The DCD registers are mapped onto memory addresses (figure 25). Port D0 is multiplexed as interrupt input pin INT0. Setting as interrupt pin is performed by bit 0 (PMR00) of port mode register 0 (PMR0: $008) (figure 26).
Data control registers (DCD0-2 : $030-$032) (DCR0-2, 7 : $034-$036, $03B) Register Name Bit Read/Write DCDn (n=0 to 2) Reset Bit name Read/Write DCRm (m=0 to 2, 7) Reset Bit name 3 W 0 DCDn3 W 0 DCRm3 All bits 0 1 2 W 0 DCDn2 W 0 DCRm2 1 W 0 DCDn1 W 0 DCRm1 CMOS buffer control CMOS buffer off (high impedance) CMOS buffer active 0 W 0 DCDn0 W 0 DCRm0
Correspondence between each bit of DCD and DCR and ports Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR7 R73 R13 R22 R72 R21 R71 Bit 3 D3 D7 Bit 2 D2 D6 Bit 1 D1 D5 D9 Bit 0 D0 D4 D8 R00 R10 R20 R70
Figure 25 Data Control Registers (DCD, DCR)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series R Port The R port consists of 10 I/O pins that are addressed in 4-bit units. Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR2, DCR7: $034 to $036, $03B). The DCR registers are mapped onto memory addresses (figure 25). Port R00 is multiplexed as wakeup input pin WU0. Setting of this pin as peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 27). Port R10 is multiplexed as peripheral function pin EVNB. Setting of this pin as peripheral function pins is performed by bit 0 (PMR20) of port mode register 2 (PMR2: $00A) (figure 28). Ports R13 and R20 are multiplexed as peripheral function pins TOB, and TOC, respectively. Setting of these pins as peripheral function pins is performed by bits 3 (PMR23) of port mode register 2 (PMR2: $00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 28 and 29). Ports R21 and R22 are multiplexed as peripheral function pins SCK and SI/SO, respectively. Setting of these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register 3 (PMR3: $00B) (figure 29). Ports R70 to R73 are multiplexed as peripheral function pins AN0 to AN3 (HD404374, HD404384, and HD404389 Series only). Setting of these pins as peripheral function pins is performed by bits 1 to 3 (AMR1 to AMR3) of the A/D mode register (AMR: $028) (see figure 64 in section 8, A/D Converter).
Port mode register 0 (PMR0: $008) Bit Read/Write Initial value on reset Bit name Not used Not used Not used 3 2 1 0 W 0 PMR00
PMR00 0 1
D0/INT0 pin mode selection D0 INT0
Figure 26 Port Mode Register 0 (PMR0: $008)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Port mode register 1 (PMR1: $009) Bit Read/Write Initial value on reset Bit name Not used Not used Not used 3 2 1 0 W 0 PMR10
PMR10 0 1
R00/WU0 pin mode selection R00 WU0
Figure 27 Port Mode Register 1 (PMR1: $009)
Port mode register 2 (PMR2: $00A) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR23 Not used Not used 2 1 0 W 0 PMR20
PMR20 0 1
R10/EVNB pin mode selection R10 EVNB
PMR23 0 1
R13/TOB pin mode selection R13 TOB
Figure 28 Port Mode Register 2 (PMR2: $00A)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Port mode register 3 (PMR3: $00B) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR33 2 W 0 PMR32 1 W 0 PMR31 0 W 0 PMR30
PMR30 0 1 PMR31 0 1 PMR33 0 1 PMR32 * 0 1 * : Don't care
R20/TOC pin mode selection R20 TOC
R21/SCK pin mode selection R21 SCK
R22/SI/SO pin mode selection R22 SI SO
Figure 29 Port Mode Register 3 (PMR3: $00B) Pull-Up MOS Control Program-controllable pull-ups MOS are incorporated in all I/O pins. On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005) and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off independently for each pin (table 22, figure 30). Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the setting as an on-chip supporting module pin.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Bit 2 of the miscellaneous register must always be set to 0. The microcomputer will malfunction if it is set to 1. Miscellaneous register (MIS: $005) Bit Read/Write Initial value on reset Bit name 3 W 0 MIS3 2 W 0 Not used* 1 W 0 MIS1 0 W 0 MIS0
tRC selection (See figure 15 in the Operating Modes section) MIS2 0 1 Setting bit2 Set to 0 Use prohibited
MIS3 0 1
pull-up MOS control All pull-ups MOS off pull-up MOS active
Note: * This bit must always be set to 0. The microcomputer will malfunction if it is set to 1.
Figure 30 Miscellaneous Register (MIS:$005) Handling of I/O Pins Not Used by User System If I/O pins that are not used by the user system are left floating, they may generate noise that can result in chip malfunctions. Therefore, the pin potential must be fixed. In this case, pull the pins up to VCC with the built-in pull-up MOS or with an external resistor of approximately 100 k.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Prescalers
The MCU has the following prescalers, S and W (HD404374 Series). The operating conditions for each prescaler are shown in table 24, and the output supply destinations in figure 31. Timer A to C input clocks other than external events, and serial transfer clocks other than external clocks are selected from the prescaler outputs in accordance with the respective mode register. Prescaler Operation Prescaler S (PSS): Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and *1 in stop mode and watch mode . It does not stop in any other modes. Prescaler W (PSW) (HD404374 Series): Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input. When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be reset by software. Table 24
Prescaler Prescaler S
Prescaler Operating Conditions
Input Clock Reset Conditions Stop Conditions MCU reset, stop mode, 1 watch mode* MCU reset, stop mode
System clock in active and MCU reset, stop mode standby modes, subsystem clearance 1 clock in subactive mode* Clock obtained by divisionby-8 of 32.768 kHz oscillation by subsystem clock oscillator MCU reset, software*
2
Prescaler W
Notes: *1 Applies to HD404374 Series *2 If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Subsystem clock HD404374 series
Prescaler W
Timer A Timer B Timer C
System clock
Clock selector
Prescaler S
Serial interface
Figure 31 Prescaler Output Destinations
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timers
The MCU incorporates three timers, A to C. * Timer A: Free-running timer * Timer B: Multifunctional timer * Timer C: Multifunctional timer Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunctional timers; Each one of their have the functions shown in table 25 and their operating mode can be set by the program. Table 25
Functios Clock source Prescaler S Prescaler W* External event Timer functions Free-running Time-base* Event counter Reload Watchdog Timer outputs Toggle PWM Note: -- implies not available * Applies to HD404374 Series
Timer Functions
Timer A Available Available -- Available Available -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- Available Available Timer C Available -- -- Available -- -- Available Available Available Available
Timer A Timer A Functions Timer A has the following functions. * Free-running timer * Realtime clock time base The block diagram of timer A is shown in figure 32.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timer A interrupt request flag (IFTA)
32.768-kHz oscillator
1/4
1/2 2 fW 1/2 t Wcyc
fW t Wcyc
Prescaler W (PSW)
/2 /8 / 16 / 32
HD404374 Series
Selector
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Data bus Clock line Signal line
Figure 32 Timer A Block Diagram Timer A Operation Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $00F). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation (HD404374 Series): Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock. When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00 by the program.
Rev.5.00, Sep.11.2003, page 70 of 161
Internal data bus
Selector
Clock
Timer counter A (TCA) Overflow
HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer A Register Timer A operation is set by means of the following register. Timer mode register A (TMA: $00F): Timer mode register A (TMA: $00F) is a 4-bit write-only register. Timer A operation and input clock selection are set as shown in figure 33.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timer mode register A (TMA: $00F) Bit Read/Write Initial value on reset Bit name 3 W 0 TMA3*4 2 W 0 TMA2 1 W 0 TMA1 0 W 0 TMA0
TMA3*4 TMA2
TMA1 0
TMA0 0 1
Source prescaler PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW PSW
Input clock period Operating mode 2,048 tcyc 1,024 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc 32 twcyc 16 twcyc 8 twcyc 2 twcyc 1/2 twcyc Time base mode Timer A mode
0 0 1 1 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 x : Don't care Notes : 1. twcyc = 244.14 s (using 32.768 kHz crystal oscillator) 2. Timer/counter overflow output period (s) = input clock period (s) x 256. 3. The division ratio must not be changed while time base mode is being used, as this will result in an error in the overflow period. 4. Applies to HD404374 Series. In HD404384, HD404389, HD404082 and HD404084 Series, write as 0. 1 x 0 1
Not Used PSW, TCA reset
Figure 33 Timer Mode Register A (TMA)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle output, PWM output) The block diagram of timer B is shown in figure 34.
Timer C clock source Timer output control logic 1 EVNB Edge detection logic 2 /2 /4
Prescaler S (PSS)
Timer B ineterrupt request flag (IFTB)
TOB
Timer read register BL (TRBL) 4
Selector
Timer read register BU (TRBU)
System clock
Free-runnning/Reload control
oPER
/32 /128 /512 /2048
(TCBL) 4
(TCBU) 4
Timer write register B (TWBL) (TWBU)
3
Timer mode register B1 (TMB1) 3
Timer mode register B2 (TMB2) Data bus Clock line Signal line
Figure 34 Timer B Block Diagram
Rev.5.00, Sep.11.2003, page 73 of 161
Internal data bus
/8
Timer counter B
Overflow
HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer B Operation * Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register B1 (TMB1). Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer B value reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. * External event counter operation: When external event input is designated for the input clock, timer B operates as an external event counter. When external event input is used, the R10/EVNB pin is designated as the EVNB pin by port mode register 2 (PMR2). The external event detected edge for timer B can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other operations are the same as for the free-running/reload timer function. * Timer output operation: With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer mode register B2 (TMB2). Toggle output: With toggle output, the output level is changed upon input of the next clock pulse after the timer B value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 35 (1). PWM output: With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 35 (2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL, TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0, the write to timer write register B to change the duty is effective from the next frame, whereas if the waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output immediately after the timer write register write. * Module standby: With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is retained but the counter value is not guaranteed.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
(1) Toggle output waveform (timer B, timer C)
Free-running timer
256 clock periods Reload timer
256 clock periods
(256 - N) clock periods
(256 - N) clock periods
(2) PWM output waveform (timer B, timer C)
T x (N + 1) TMB13 = 0 TMC13 = 0 (free-running timer) T x 256 T TMB13 = 1 TMC13 = 1 (reload timer) T x (256 - N)
Notes:
T: Counter input clock period The clock input source and division ratio are controlled by timer mode register B1 and timer mode register C1. N: Value in timer write register B or timer write register C When N = 255 (= $FF), PWM output is always fixed at the timer low level.)
(
)
Figure 35 Timer Output Waveforms
Rev.5.00, Sep.11.2003, page 75 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer B Registers Timer B operation setting and timer B value reading/writing is controlled by the following registers. Timer mode register B1 (TMB1: $010) Timer mode register B2 (TMB2: $011) Timer write register B (TWBL: $012, TWBU: $013) Timer read register B (TRBL: $012, TRBU: $013) Port mode register 2 (PMR2: $00A) Module standby register 1 (MSR1: $00D) * Timer mode register B1 (TMB1: $010): Timer mode register B1 (TMB1) is a 4-bit write-only register, used to select free-running/reload timer operation and the input clock as shown in figure 36. Timer mode register B1 (TMB1) is reset to $0 by an MCU reset: A modification of timer mode register B1 (TMB1) becomes effective after execution of two instructions following the timer mode register B1 (TMB1) write instruction. The program must provide for timer B initialization by writing to timer write register B (TWBL, TWBU) to be executed after the postmodification mode has become effective.
Timer mode register B1 (TMB1: $010) Bit Read/Write Initial value on reset Bit name 3 W 0 TMB13 2 W 0 TMB12 1 W 0 TMB11 0 W 0 TMB10
TMB12
TMB11 0
TMB10 0 1
Input clock period and input clock source 2,048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc R10/EVNB (external event input)
0 1 0 1 1
0 1 0 1 0 1
TMB13 0 1
Free-running/reload timer Free-running timer Reload timer
Figure 36 Timer Mode Register B1 (TMB1)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series * Timer mode register B2 (TMB2: $011): Timer mode register B2 (TMB2) is a 3-bit write-only register, used to select the timer B output mode and EVNB pin detected edge as shown in figure 37. Timer mode register B2 (TMB2) is reset to $0 by an MCU reset.
Timer mode register B2 (TMB2: $011) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 TMB22 1 W 0 TMB21 0 W 0 TMB20
TMB21 TMB20 0 0 1 1 TMB22 0 1 0 1
EVNB pin detected edge Not detected Falling edge detection Rising edge detection Both rising and falling edge detection
Timer B output waveform Toggle output PWM output
Figure 37 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $012, TWBU:$013): Timer write register B (TWBL, TWBU) is a write-only register composed of a lower digit (TWBL) and an upper digit (TWBU) (figures 38 and 39). The lower digit (TWBL) of timer write register B is reset to $0 by an MCU reset, while the upper digit (TWBU) is undetermined. Timer B can be initialized by writing to timer write register B (TWBL, TWBU). To write the data, first write the lower digit (TWBL). The lower digit write does not change the timer B value. Next, write the upper digit (TWBU). Timer B is then initialized to the timer write register B (TWBL, TWBU) value. When writing to timer write register B (TWBL, TWBU) from the second time onward, if it is not necessary to change the lower digit (TWBL) reload value, timer B initialization is completed by the upper digit write alone.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timer write register B (lower) (TWBL: $012) Bit Read/Write Initial value on reset Bit name 3 W 0 TWBL3 2 W 0 TWBL2 1 W 0 TWBL1 0 W 0 TWBL0
Figure 38 Timer Write Register B (Lower) (TWBL)
Timer write register B (upper) (TWBU: $013) Bit Read/Write Initial value on reset Bit name 3 W 2 W 1 W 0 W
Undetermined Undetermined Undetermined Undetermined
TWBU3
TWBU2
TWBU1
TWBU0
Figure 39 Timer Write Register B (Upper) (TWBU) * Timer read register B (TRBL: $012, TRBU: $013): Timer read register B (TRBL, TRBU) is a read-only register composed of a lower digit (TRBL) and an upper digit (TRBU) from which the value of the upper digit of timer B is read directly (figures 40 and 41). First, read the upper digit (TRBU) of timer read register B. The current value of the timer B upper digit is read and, at the same time, the value of the timer B lower digit is latched in the lower digit (TRBL) of timer read register B. The timer B value is obtained when the upper digit (TRBU) of timer read register B is read by reading the lower digit (TRBL) of timer read register B.
Timer read register B (lower) (TRBL: $012) Bit Read/Write Initial value on reset Bit name 3 R TRBL3 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined
TRBL2
TRBL1
TRBL0
Figure 40 Timer Read Register B (Lower) (TRBL)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timer read register B (upper) (TRBU: $013) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined
TRBU3
TRBU2
TRBU1
TRBU0
Figure 41 Timer Read Register B (Upper) (TRBU) * Port mode register 2 (PMR2: $00A): Port mode register 2 (PMR2) is a write-only register used to set the function of the R10/EVNB and R13/TOB pins as shown in figure 42. Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
Port mode register 2 (PMR2: $00A) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR23 2 -- -- Not used 1 -- -- Not used 0 W 0 PMR20
PMR20 0 1 PMR23 0 1 R13/TOB pin mode selection R13 TOB
R10/EVNB pin mode selection R10 EVNB
Figure 42 Port Mode Register 2 (PMR2: $00A) * Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer B as shown in figure 43. Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Module standby register 1 (MSR1: $00D) Bit Read/Write Initial value on reset Bit name 3 -- -- Not used 2 -- -- Not used
1
W 0 MSR11
0 W 0 MSR10
MSR10 0 1 MSR11 0 1
Timer B clock supply control Supplied Stopped
Timer C clock supply control Supplied Stopped
Figure 43 Module Standby Register 1 (MSR1)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer C Timer C Functions:Timer : C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle output, PWM output) The block diagram of timer C is shown in figure 44.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
System reset signal Watchdog on flag (WDON) TOC Timer output control logic
Timer C interrupt request flag (IFTC)
Watchdog timer control logic
System clock
PER
Timer B overflow
Timer read register CL (TRCL)
Timer read register CU (TRCU)
4
Prescaler (PSS)
32 128 512 2048
Free-running/reload control
Selector
(TCCL) 4
(TCCU) 4
Timer write register C
(TWCL)
(TWCU)
3
Timer mode register C1 (TMC1)
Timer output control Data bus Clock line Signal line
Timer mode register C2 (TMC2)
Figure 44 Timer C Block Diagram
Rev.5.00, Sep.11.2003, page 82 of 161
Internal data bus
8
Timer counter C
Overflow
2
4
HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer C Operation * Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register C1 (TMC1). Timer C is initialized to the value written to timer write register C (TWCL, TWCU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer C value reaches $FF, overflow output is generated. Timer C is then set to the value in timer write register C (TWCL, TWCU) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer C interrupt request flag (IFTC). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. * 16-bit timer operation: When timer B overflow flag is selected as the clock source, timer C can be used as a 16-bit timer that counts the timer B clock source pulses. In this case, since the timer B and timer C free-running/reload settings are independent, the settings should be made to suit the purpose. * Watchdog timer operation: By using the timer C overflow output, timer C can be used as a watchdog timer for detecting program runaway. The watchdog timer is enabled when the watchdog on flag (WDON) is set to 1, and generates an MCU reset when timer C overflows. Usually, timer C initialization is performed by the program before the timer C value reaches $FF, so controlling program runaway. * Timer output operation: With timer C, the R20/TOC pin is designated as the TOC pin by setting bit 0 of port mode register 3 (PMR3) to 1, and toggle waveform output or PWM waveform output can be selected by timer mode register C2 (TMC2). Toggle output The operation is similar to that for timer B toggle output. PWM output The operation is similar to that for timer B PWM output. * Module standby: The operation is similar to that for timer B module standby.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer C Registers Timer C operation setting and timer C value reading/writing is controlled by the following registers. Timer mode register C1 (TMC1: $014) Timer mode register C2 (TMC2: $015) Timer write register C (TWCL: $016, TWCU: $017) Timer read register C (TRCL: $016, TRCU: $017) Port mode register 3 (PMR3: $00B) Module standby register 1 (MSR1: $00D) * Timer mode register C1 (TMC1: $014): Timer mode register C1 (TMC1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 45. Timer mode register C1 (TMC1) is reset to $0 by an MCU reset. A modification of timer mode register C1 (TMC1) becomes effective after execution of two instructions following the timer mode register C1 (TMC1) write instruction. The program must provide for timer C initialization by writing to timer write register C (TWCL, TWCU) to be executed after the postmodification mode has become effective.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timer mode register C1 (TMC1: $014) Bit Read/Write Initial value on reset Bit name 3 W 0 TMC13 2 W 0 TMC12 1 W 0 TMC11 0 W 0 TMC10
TMC12
TMC11 0
TMC10 0 1 0
Input clock period 2,048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc Timer B overflow
0 1
1 0
0 1 1
1 0 1
TMC13 0 1
Free-running/reload timer Free-running timer Reload timer
Figure 45 Timer Mode Register C1 (TMC1)
Rev.5.00, Sep.11.2003, page 85 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series * Timer mode register C2 (TMC2: $015): Timer mode register C2 (TMC2) is a 1-bit write-only register, used to select the timer C output mode as shown in figure 46. Timer mode register C2 (TMC2) is reset to $0 by an MCU reset.
Timer mode register C2 (TMC2: $015) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 TMC22 1 -- -- -- 0 -- -- --
TMC22 0 1
Timer C output waveform Toggle output PWM output
Figure 46 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $016, TWCU: $017): Timer write register C (TWCL, TWCU) is a write-only register composed of a lower digit (TWCL) and an upper digit (TWCU) (figures 47 and 48). Timer write register C (TWCL, TWCU) operation is similar to that for timer write register B (TWBL, TWBU).
Timer write register C (lower) (TWCL: $016) Bit Read/Write Initial value on reset Bit name 3 W 0 TWCL3 2 W 0 TWCL2 1 W 0 TWCL1 0 W 0 TWCL0
Figure 47 Timer Write Register C (Lower) (TWCL)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Timer write register C (upper) (TWCU: $017) Bit Read/Write Initial value on reset Bit name 3 W 2 W 1 W 0 W
Undetermined Undetermined Undetermined Undetermined TWCU3 TWCU2 TWCU1 TWCU0
Figure 48 Timer Write Register C (Upper) (TWCU) * Timer read register C (TRCL: $016, TRCU: $017): Timer read register C (TRCL, TRCU) is a read-only register composed of a lower digit (TRCL) and an upper digit (TRCU) from which the value of the upper digit of timer C is read directly (figures 49 and 50). Timer read register C (TRCL, TRCU) operation is similar to that for timer read register B (TRBL, TRBU).
Timer read register C (lower) (TRCL: $016) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined TRCL3 TRCL2 TRCL1 TRCL0
Figure 49 Timer Read Register C (Lower) (TRCL)
Timer read register C (upper) (TRCU: $017) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined TRCU3 TRCU2 TRCU1 TRCU0
Figure 50 Timer Read Register C (Upper) (TRCU)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series * Port mode register 3 (PMR3: $00B): Port mode register 3 (PMR3) is a write-only register used to set the function of the R20/TOC pin as shown in figure 51. Port mode register 3 (PMR3) is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR33 2 W 0 PMR32 1 W 0 PMR31 0 W 0 PMR30
PMR30 0 1 PMR31 0 1 PMR33 0 1 PMR32 0 1 : Don't care R21/
R20/TOC pin mode selection R20 TOC
pin mode selection R21 SCK
R22/SI/SO pin mode selection R22 SI SO
Figure 51 Port Mode Register 3 (PMR3) * Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer C as shown in figure 43. Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. * Serial data register (SRL: $026, SRU: $027) * Serial mode register 1 (SMR1: $024) * Serial mode register 2 (SMR2: $025) * Port mode register 3 (PMR3: $00B) * Octal counter (OC) * Selector The block diagram of the serial interface is shown in figure 52.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Octal counter (OC)
Serial interrupt request flag (IFS)
SI/SO
Idle control logic
SCK
I/O control logic
Clock
Serial data register (SRL/U)
Internal data bus
2
Selector
System clock
PER
1/2
Transfer control
PrescalerS (PSS)
2 8 32 128 512 2048
1/2
Selector
4
Serial mode register 1 (SMR1)
Data bus Clock line Signal line
Serial mode register 2 (SMR2)
Figure 52 Serial Interface Block Diagram
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial Interface Operation Selecting and changing serial interface operating mode: The operating modes that can be selected for the serial interface are shown in table 26. The combination of port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1 (SMR1). Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See figure 56 Serial Mode Register 1, for details. Table 26
PMR3 Bit3 0 1 1 Bit2 * 0 1 Bit1 1 1 1 Serial interface operating mode Clock continuous output mode Receive mode Transmit mode
Serial Interface Operating Modes
Note : * Don't care
Serial interface pin setting: The R21/SCK pin and R22/SI/SO pin are set by writing data to port mode register 3 (PMR3). See Serial Interface Registers, for details. Serial clock source setting: The serial clock is set by writing data to serial mode register 1 (SMR1). See Serial Interface Registers, for details. Serial data setting: Transmit serial data is set by writing data to the serial data register (SRL, SRU). Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by means of the serial clock to perform input/output from/to an external device. The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or until high/low control is performed in the idle state. Transfer control: Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial interrupt request flag (IFS) is set, and transfer is terminated. The serial clock is selected by means of serial mode register 1 (SMR1). See figure 56.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial interface operating states: The serial interface has the operating states shown in figure 53 in external clock mode and internal clock mode. STS instruction wait state Serial clock wait state Transfer state Clock continuous output state (internal clock mode only) * STS instruction wait state Upon MCU reset ((00) and (10) in figure 53), the serial interface enters the STS instruction wait state. In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial clock is input at this time, the serial interface will not operate. When the STS instruction is executed ((01), (11)), the serial interface enters the serial clock wait state. * Serial clock wait state The serial clock wait state is the interval from STS instruction execution until the first serial clock falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter begins counting, the contents of the serial data register (SRL, SRU) begin shifting, and the serial interface enters the transfer state. However, if clock continuous output mode is selected in internal clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer state. If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface enters the STS instruction wait state ((04), (14)). * Transfer state The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and enters the STS instruction wait state ((13)) when in internal clock mode. In internal clock mode, the serial clock stops after output of eight clocks. If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial interface is initialized and enters the STS instruction wait state. When the serial interface switches from the transfer state to another state, the octal counter is reset to 000 and the serial interrupt request flag (IFS) is set. * Clock continuous output state (internal clock mode only) In the clock continuous output state, no receive or transmit operation is performed, and the serial clock is only output from the SCK pin. It is therefore effective in internal clock mode. If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and the serial interface is in the serial clock wait state, a transition is made to the clock continuous output state. If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the serial interface enters the STS instruction wait state.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
MCU reset (00)
STS instruction wait state (octal counter ="000", serial clock disabled)
SMR1 write (04) STS instruction (01)
SMR1 write (06) (IFS "1")
Serial clock (02) Serial clock wait state (octal counter ="000") 8 serial clocks (03) STS instruction (05) (IFS "1") External clock mode Transfer state (octal counter "000")
MCU reset (10) SMR1 write (18)
STS instruction wait state (octal counter ="000", serial clock disabled)
Clock continuous output state (PMR33 ="0") SMR1 write (14) Serial clock (17) Serial clock (12) Serial clock wait state (octal counter ="000") STS instruction (15) (IFS"1") Internal clock mode ( ) Refer to the text for details on the circled numbers in the figure. STS instruction (11)
8 serial clocks (13) SMR1 write (16) (IFS"1")
Transfer state (octal counter "000")
Figure 53 Serial Interface Operating States
Rev.5.00, Sep.11.2003, page 93 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Idle high/low control: When the serial interface is in the STS instruction wait state or the serial clock wait state (i.e. when idle), the output level of the SO pin can be set arbitrarily by software. Idle high/low control is performed by writing the output level to bit 1 (SMR21) of serial mode register 2 (SMR2). An example of idle high/low control is shown in figure 54. Idle high/low control cannot be performed in the transfer state.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Serial clock wait state State MCU reset PMR3 write SMR1 write SMR2 write SRL, SRU write STS instruction pin (input) SO pin Undefined Idle
LSB
Serial clock wait state Transfer state STS wait state
STS wait state
Port setting External clock setting Idle H/L setting Transmit data write Dummy write to cause state transition Idle H/L setting
MSB
Idle
IFS (1) External clock mode (Flag reset by transfer completion processing)
Serial clock wait state State MCU reset PMR3 write SMR1 write SMR2 write SRL, SRU write STS instruction pin (output) SO pin Undefined Idle
LSB
STS wait state
Transfer state
STS wait state
Port setting External clock setting Idle H/L setting Transmit data write Idle H/L setting
MSB
Idle
IFS (2) Internal clock mode (Flag reset by transfer completion processing)
Figure 54 Examples of Serial Interface Operation Sequence
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial clock error detection (external clock mode): The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in figure 55. If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial clock wait state, but returns to the transfer state at the next regular clock pulse falling edge. Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy write to serial mode register 1. Usage notes: * Initialization after register modification If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a serial mode register 1 (SMR1) write should be performed again to initialize the serial interface. * Serial interrupt request flag (IFS:$023, 2) setting If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to make sure that the SCK pin is in the 1 state (by executing an input instruction for the R2 port) before executing a serial mode register 1 (SMR1) write or an STS instruction.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Transfer end (IFS"1")
Disable interrupts
IFS"0"
SMR1 write
Yes IFS=1? No Normal termination
Serial clock error processing
(1) Serial clock error detection flowchart
Serial clock wait state State
Serial clock wait state Transfer state Transfer state
SCK pin (input) (Noise) 1 2 3 4 5 6 7 8 Because the serial interface returns to the transfer state, a write to SMR1 resets IFS.
SMR1 write
IFS Flag set by octal counter reaching 000 (2) Serial clock error detection sequence Flag reset by transfer end processing
Figure 55 Example of Serial Clock Error Detection
Rev.5.00, Sep.11.2003, page 97 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial Interface Registers Serial interface operation setting and serial data reading/writing is controlled by the following registers. Serial mode register 1 (SMR1: $024) Serial mode register 2 (SMR2: $025) Serial data register (SRL: $026, SRU: $027) Port mode register 3 (PMR3: $00B) Module standby register 2 (MSR2: $00E) Serial mode register 1 (SMR1: $024): Serial mode register 1 (SMR1) has the following functions. See figure 56. * Serial clock selection * Prescaler division ratio selection * Serial interface initialization The serial mode register 1 (SMR1) is a 4-bit write-only register, and is reset to $0 by an MCU reset. A write to serial mode register 1 (SMR1) halts the supply of the serial clock to the serial data register (SRL, SRU) and the octal counter, and resets the octal counter to 000. Therefore, if serial mode register 1 (SMR1) is written to during serial interface operation, data transmission/reception will be suspended and the serial interrupt request flag (IFS) will be set. A modification of serial mode register 1 (SMR1) becomes effective after execution of two instructions following the serial mode register 1 (SMR1) write instruction. The program must therefore provide for the STS instruction to be executed two cycles after the instruction that writes to serial mode register 1 (SMR1).
Rev.5.00, Sep.11.2003, page 98 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Serial mode register 1 (SMR1: $024) Bit Read/Write Initial value on reset Bit name 3 W 0 2 W 0 1 W 0 0 W 0
SMR13 SMR12 SMR11 SMR10
SMR13 SMR12 SMR11 SMR10 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0
Serial clock Serial clock SCK pin Serial clock source (PSS division ratio + 2 or 4) cycle Output Output Output Output Output Output Output Input Output Output Output Output Output Output Output Input PSS PSS PSS PSS PSS PSS System clock External clock PSS PSS PSS PSS PSS PSS System clock External clock ( ( ( ( ( (
PER/2048)+4 PER/512)+4 PER/128)+4 PER/32)+4 PER/8)+4 PER/2)+4 PER
( ( ( ( ( (
PER/2048)+2 PER/512)+2 PER/128)+2 PER/32)+2 PER/8)+2 PER/2)+2 PER
4096 tcyc 1024 tcyc 256 tcyc 64 tcyc 16 tcyc 4 tcyc tcyc
8192 tcyc 2048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc tcyc
Figure 56 Serial Mode Register 1 (SMR1) Serial mode register 2 (SMR2: $025): Serial mode register 2 (SMR2) has the following functions. See figure 57. * R22/SI/SO pin PMOS control * Idle high/low control Serial mode register 2 (SMR2) is a 2-bit write-only register. The register value cannot be modified in the transfer state. Bit 2 (SMR22) of serial mode register 2 (SMR2) controls the on/off status of the R22/SI/SO pin PMOS. The bit 2 (SMR22) only is reset to 0 by an MCU reset. Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The SO pin changes at the same time as the high/low write.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Serial mode register 2 (SMR2: $025) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 1 W
undeternined
0 -- --
SMR22 SMR21
SMR21 0 1 SMR22 0 1
Idle high/low control SO pin set to low-level output in idle state SO pin set to high-level output in idle state
R22/SI/SO pin output buffer control PMOS active PMOS off (NMOS open-drain output)
Figure 57 Serial Mode Register 2 (SMR2) Serial data register (SRL: $026, SRU: $027): The serial data register (SRL, SRU) has the following functions. See figures 58 and 59. * Transmit data write and shift operations * Receive data shift and read operations The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in synchronization with the falling edge of the serial clock. External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial clock. Figure 60 shows the serial clock and data input/output timing chart. Writing and reading of the serial data register (SRL, SRU) must be performed only after data transmission/reception is completed. The data contents are not guaranteed if a read or write is performed during data transmission or reception.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Serial data register (lower) (SRL: $026) Bit Read/Write Bit name 3 R/W SR3 2 R/W SR2 1 R/W SR1 0 R/W SR0
Initial value on reset Undetermined Undetermined Undetermined Undetermined
Figure 58 Serial Data Register (SRL)
Serial data register (upper) (SRU: $027) Bit Read/Write Bit name 3 R/W SR7 2 R/W SR6 1 R/W SR5 0 R/W SR4
Initial value on reset Undetermined Undetermined Undetermined Undetermined
Figure 59 Serial Data Register (SRU)
Serial clock 1 Serial output data Serial input data latch timing LSB 2 3 4 5 6 7 8 MSB
Figure 60 Serial Interface Input/Output Timing Chart
Rev.5.00, Sep.11.2003, page 101 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Port mode register 3 (PMR3: $00B): Port mode register 3 (PMR3) has the following functions. See figure 61. * R21/SCK pin selection * R22/SI/SO pin selection Port mode register 3 (PMR3) is a 4-bit write-only register used to select serial interface pin settings as shown in figure 61. It is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B) Bit Read/Write Initial value on reset Bit name 3 W 0 2 W 0 1 W 0 0 W 0
PMR33 PMR32 PMR31 PMR30
PMR30 R20/TOC pin mode selection 0 1 R20 TOC
PMR31 R21/SCK pin mode selection 0 1 R21 SCK
PMR33 PMR32 R22/SI/SO pin mode selection 0 1 0 1 R22 SI SO
: Don't care
Figure 61 Port Mode Register 3 (PMR3)
Rev.5.00, Sep.11.2003, page 102 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Module standby register 2 (MSR2: $00E): Module standby register 2 (MSR2) is a write-only register used to designate supply or stopping of the clock to the serial interface as shown in figure 62. Module standby register 2 (MSR2) is reset to $0 by an MCU reset.
Module standby register 2 (MSR2: $00E) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 -- -- -- 1 W 0 0 W 0
MSR21 MSR20
MSR20 Serial clock supply control 0 1 Supplied Stopped
MSR21 A/D clock supply control 0 1 Supplied Stopped
Figure 62 Module Standby Register 2 (MSR2)
Rev.5.00, Sep.11.2003, page 103 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
A/D Converter (HD404374/HD404384/HD404389 Series)
The MCU has a built-in successive approximation type A/D converter using a resistance ladder method, capable of digital conversion of four analog inputs with an 10-bit resolution. The A/D converter block diagram is shown in figure 63. The A/D converter comprises the following four registers. * A/D mode register (AMR: $028) * A/D start flag (ADSF: $020,2) * A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B) * Module standby register 2 (MSR2: $00E) Note : With the HD404374, HD404384, and HD404389 Series emulator, write 1 to bit 0 (ADRL0) of A/D TM data register-lower (ADRL). This bit need not be written in the mask ROM and ZTAT versions in these series, although writing 1 will have no effect.
Interrupt flag (IFAD)
Encoder
A/D data register (ADRU, ADRM, ADRL)
3
R70/AN0 R71/AN1 R72/AN2 R73/AN3 *AN4 *AN5
Selector
A/D mode register (AMR)
+
COMP
-
A/D control logic
Conversion time control
AVCC
Reference voltage
Reference voltage control
A/D start flag (ADSF) Operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby)
AVSS
D/A
Note: * Applies to HD404389 Series.
Figure 63 A/D Converter Block Diagram
Rev.5.00, Sep.11.2003, page 104 of 161
Internal data bus
HD404374/HD404384/HD404389/HD404082/HD404084 Series A/D mode register (AMR: $028): The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 64). A/D start flag (ADSF: $020,2): A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 65).
A/D mode register (AMR: $028) Bit Read/Write Initial value on reset Bit name 3 W 0 AMR3 2 W 0 AMR2 1 W 0 AMR1 0 W 0 AMR0
AMR0 A/D conversion time 0 1 65 tcyc 125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection 0 0 1 -- 0 1 0 0 1 1 1 0 1 No selection AN0 AN1 AN2 AN3 AN4* AN5*
Note: * Applies to the HD404389 series. This selection is not available on the HD 404374 and HD404384 series.
Figure 64 A/D Mode Register (AMR)
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
A/D start flag (ADSF: $020,2) Bit Read/Write Initial value on reset Bit name 3 R/W 0 DTON 2 R/W 0 ADSF 1 R/W 0 WDON 0 R/W 0 LSON
LSON (see low-power mode section) WDON (see timer section) A/D start flag (ADSF) 1 0 A/D conversion starts Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 65 A/D Start Flag (ADSF) A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B): The A/D data register is a read-only register consisting of a middle 4 bits and lower 2 bits. This register is not cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion, the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts (figures 66, 67, 68, and 69).
ADRU : $02B 3 2 1 0 3
ADRM : $02A 2 1 0
ADRL : $029 3 2
MSB bit9
LSB bit0
Figure 66 A/D Data Register
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
A/D data register-lower (ADRL: $029) Bit Read/Write Initial value on reset Bit name 3 R 1 ADRL3 2 R 1 ADRL2 1 -- -- Not used 0 -- --* Not used
Note: * Should be written with 1 with the emulator.
Figure 67 A/D Data Register-Lower (ADRL)
A/D data register-middle (ADRM: $02A) Bit Read/Write Initial value on reset Bit name 3 R 1 ADRM3 2 R 1 ADRM2 1 R 1 ADRM1 0 R 1 ADRM0
Figure 68 A/D Data Register-Middle (ADRM)
A/D data register-upper (ADRU: $02B) Bit Read/Write Initial value on reset Bit name 3 R 0 ADRU3 2 R 1 ADRU2 1 R 1 ADRU1 0 R 1 ADRU0
Figure 69 A/D Data Register-Upper (ADRU) Module standby register 2 (MSR2: $00E): Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and cuts the current (IAD) flowing in the ladder resistor.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Usage notes: * Use the SEM or SEMD instruction to write to the A/D start flag (ADSF). * Do not write to the ADSF during A/D conversion. * Data in the A/D data register is undetermined during A/D conversion. * As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to reduce power consumption. * When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is disabled. * Use of bit 0 of A/D data register-lower (ADRL) is prohibited, but with the emulator it should be written TM with 1. This bit need not be written in the mask ROM and ZTAT versions, although writing 1 will have no effect.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
ZTAT
TM
Microcomputer with Built-in Programmable ROM
Precautions for use of ZTATTM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTATTM microcomputer In the ZTAT microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer, power source current capacity of VPP, and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-VCC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting
TM
Rev.5.00, Sep.11.2003, page 109 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the RESET and MO terminals to "Low" level and the TEST terminal to "Vpp" level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM writer with a general-purpose PROM, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 70.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 29. If it is programmed erroneously to an address given in table 29 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product employs a VPP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258 specifications. Table 27
Package FP-30D DP-28S
Socket Adapters
Model Name Please ask Renesas Technology service section. Please ask Renesas Technology service section. Manufacturer
Writing/Verification
Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure 71 and a timing chart in figure 72. For precautions for PROM writing procedure, refer to "Precautions for use of ZTAT microcomputer with build-in programmable ROM". Table 28
Mode Writing Verification Prohibition of programming
TM
Selection of Mode
CE "Low" "High" "High" OE "High" "Low" "High" VPP VPP VPP VPP O0 to O4 Data input Data output High impedance
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 29
ROM size 2k 4k 8k 16k
PROM Writer Program Address
Address $0000~$0FFF $0000~$1FFF $0000~$3FFF $0000~$7FFF
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Programmable ROM
The HD407A4374/HD407C4374/HD407A4384/HD407C4384, HD407A4389/HD407C4389 are ZTAT microcomputers with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description (1) HD407A4374/HD407C4374/HD407A4384/HD407C4384
Pin No. FP-30D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DP-28S 1 2 3 4 5 6 7 8 9 10 11 -- -- 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MCU Mode Pin name GND VCC AVCC R70/AN0 R71/AN1 R72/AN2 R73/AN3 AVSS OSC1 OSC2 TEST X2 X1 RESET R00/WU0 R10/EVNB R13/TOB R20/TOC R21/SCK R22/SI/SO D0/INT0 D1 D2 D3 D4 D5 D6 D7 D8 D9 I/O -- -- -- I/O I/O I/O I/O -- I O I O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode. Pin name GND VCC VCC O0 O1 O2 O3 GND A0 -- VPP -- GND RESET A1 A2 O4 CE A2 A3 MO A5 A6 A7 A8 A9 A10 A11 A12 OE I/O -- -- -- I/O I/O I/O I/O -- I -- -- -- -- I I I I/O I I I I I I I I I I I I I
TM
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HD404374/HD404384/HD404389/HD404082/HD404084 Series (2) HD407A4389 and HD407C4389
Pin No. FP-30D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Note: MCU Mode Pin name GND VCC AVCC R70/AN0 R71/AN1 R72/AN2 R73/AN3 AN4 AN5 AVSS TEST OSC1 OSC2 RESET R00/WU0 R10/EVNB R13/TOB R20/TOC R21/SCK R22/SI/SO D0/INT0 D1 D2 D3 D4 D5 D6 D7 D8 D9 I/O -- -- -- I/O I/O I/O I/O I I -- I I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode. Pin name GND VCC VCC O0 O1 O2 O3 CE OE GND VPP A0 -- RESET A1 A4 O4 A14 A2 A3 MO A5 A6 A7 A8 A9 A10 A11 A12 A13 -- I -- I I I I/O I I I I I I I I I I I I I I/O -- -- -- I/O I/O I/O I/O I I
I/O: I/O pin, I: Input-only pin, O: Output-only pin
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
1. Unused data pins (O5 to O7) on the PROM programmer side should be handled as shown below on the socket.
VCC
O5, O6, O7
2. Pin A9 should be handled as shown below on the socket.
VCC
A9 HD407A4374 HD407C4374 HD407A4384 HD407C4384 HD407A4389 HD407C4389
Writer side
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Pin Functions in PROM Mode VPP: Applies the on-chip PROM programming voltage (12.5 V 0.3 V). CE: CE Inputs a control signal to set the on-chip PROM to the write/verify enabled state. OE: OE Inputs a data output control signal during verification. A0 to A14: On-chip PROM address input pins. O0 to O4: On-chip PROM data bus I/O pins. MO, RESET, TEST: MO RESET PROM mode setting pins. PROM mode is set by driving the RESET, and MO pins low, and driving the TEST pin to the VPP level. Other pins: VCC and AVCC should be connected to VCC potential. GND, AVSS, and X1 should be connected to GND potential. Other pins should be left open.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
$0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . $1FFF $2000 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits
$0000
Vector address
$000F $0010
JMPL instruction routine) (jump to JMPL instruction (jump to 0 routine) JMPL instruction 0 routine) (jump to
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
Zero-page subroutine (64 words)
$003F $0040
Pattern (4,096 words)
$07FF $0800
JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to timer C routine) JMPL instruction (jump to A/D, serial routine)
Program (16,384 words)
$7FFF
$3FFF
Upper three bits are not to be used (fill them with 111)
Figure 70 Memory Map in PROM Mode
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Start Set Prog./Verify Mode VPP=12.50.3V, VCC=6.00.25V Address=0 n=0 Yes n+1n No S=25 NoGo Verify Go Program tOPW = 3nms Last Address? Yes Set Read Mode VCC=5.00.5V, VPP=VCC0.6V NoGo Read All Address Go Fail End No Address + 1Address nFigure 71 Flowchart of High-Speed Programming
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Programming Electrical Characteristics DC Characteristics (VCC = 6V 0.25V, VPP = 12.5V 0.3V, VSS = 0V, Ta = 25C 5C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage O0 to O4,A0 to A14, OE, CE O0 to O4,A0 to A14, OE, CE O0 to O4 O0 to O4 Symbol VIH VIL VOH VOL IIL ICC IPP IOH=-200A IOL=1.6mA Vin=5.25V/0.5V Test Conditions min 2.2 -0.3 2.4 -- -- -- -- typ -- -- -- -- -- -- -- max Unit
VCC+0.3 V 0.8 -- 0.4 2 30 40 V V V A mA mA
Input leakage current O0 to O4,A0 to A14, OE, CE VCC current VPP current
AC Characteristics (VCC = 6V 0.25V, VPP = 12.5V 0.3V, Ta = 25C 5C, unless otherwise specified)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Program pulse width CE pulse width during overprogramming VCC setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF tVPS tPW tOPW tVCS tOE Test Conditions See figure 72 min 2 2 2 0 2 -- 2 0.95 2.85 2 0 typ -- -- -- -- -- -- -- 1.0 -- -- -- max -- -- -- -- -- 130 -- 1.05 78.75 -- 500 Unit s s s s s ns s ms ms s ns
Notes: Input pulse level: 0.8 V to 2.2 V Input rise/fall times: 20ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Program Address tAS Data tDS VPP VPP VCC tVPS Data In Stable tDH
Verify
tAH Data Out Valid tDF
VCC VCC GND
tVCS
CE
tPW tOES tOE
OE
tOPW
Figure 72 PROM Write/Verify Timing
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTATTM microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 73). The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: * Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. * Heat excites trapped electrons, allowing them to escape. * High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage.
Control gate
Control gate
SiO2 Source N+
Floating gate Drain
SiO2 Source N+
Floating gate Drain
N+
N+
Write (0)
Erasure (1)
Figure 73 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse tPW is applied, the more electrons are injected into the floating gates. However, if VPP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTATTM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: * Check that the socket adapter is firmly mounted on the PROM programmer. * Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTATTM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150C at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 74. Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter. If programming verification indicates errors in programming or after high-temperature exposure, please inform Renesas Technology.
Programming, verification
Exposure to high temperature, without power 150C 10C, 48 h +8h* -0h
Program read check VCC = 4.5 V or 5.5 V Note: * Exposure time is measured from when the temperature in the heater reaches 150C.
Figure 74 Recommended Screening Procedure Programming percentage: Programming percentage is guarenteed to more than 95%.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 75 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Indirect Addressing
1st word of Instruction Opcode d
9
2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 75 RAM Addressing Modes
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HD404374/HD404384/HD404389/HD404082/HD404084 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 76 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 78. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross assembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 77. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. Branch Destination of BR Instruction on Page Boundary: If a BR instruction is located on a page boundary (256n + 255), because of the hardware architecture the program counter contents will shift to the next page when that instruction is executed. When using a BR instruction on a page boundary, therefore, the branch destination must be set within the next page (see figure 78). The HMCS400-series cross assembler has an automatic paging feature for ROM pages, regardless of the model.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0
[JMPL] [BRL] [CALL]
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0
0 Program counter
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 76 ROM Addressing Modes
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
Note: Designate RO9 as 0. Cannot assign pattern output to port R.
Figure 77 P Instruction
256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 78 Branching when the Branch Destination is on a Page Boundary
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Instruction Set
The MCU Series has 101 instructions, classified into the following 10 groups: * Immediate instructions * Register-to-register instructions * RAM addressing instructions * RAM register instructions * Arithmetic instructions * Compare instructions * RAM bit manipulation instructions * ROM addressing instructions * Input/output instructions * Control instructions The functions of these instructions are listed in tables 30 to 39, and an opcode map is shown in table 40. Table 30
Operation Load A from immediate Load B from immediate Load memory from immediate Load memory from immediate, increment Y
Immediate Instructions
Mnemonic LAI i LBI i LMID i,d LMIIY i Operation Code 1 0 0 0 1 1 i3 1 0 0 0 0 0 i3 i2 i2 i1 i1 i0 i0 Function iA iB iM i M, Y + 1 Y NZ Status Words/ Cycles 1/1 1/1 2/2 1/1
0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 0 1 i3 i2 i1 i0
Table 31
Operation Load A from B Load B from A Load A from W Load A from Y
Register-Register Instructions
Mnemonic LAB LBA LAW LAY LASPX LASPY LAMR m XMRA m Operation Code 0001001000 0011001000 0100000000 0000000000 0010101111 0001101000 0001011000 1 0 0 1 1 1 m3 m2 m1 m0 1 0 1 1 1 1 m3 m2 m1 m0 Function BA AB WA YA SPX A SPY A MR (m) A MR (m) A Status Words/ Cycles 1/1 1/1 2/2* 1/1 1/1 1/1 1/1 1/1
Load A from SPX Load A from SPY Load A from MR Exchange MR and A
Note: * The assembler automatically provides an operand for the second word of the LAW instruction.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 32
Operation Load W from immediate Load X from immediate Load Y from immediate Load W from A Load X from A Load Y from A Increment Y Decrement Y Add A to Y Subtract A from Y Exchange X and SPX Exchange Y and SPY Exchange X and SPX, Y and SPY
RAM Address Instructions
Mnemonic LWI i LXI i LYI i LWA* LXA LYA IY DY AYY SYY XSPX XSPY XSPXY Operation Code 0 0 1 1 1 1 0 0 i1 1 0 0 0 1 0 i3 1 0 0 0 0 1 i3 i2 i2 i1 i1 i0 i0 i0 Function iW iX iY AW AX AY Y+1Y Y-1Y Y+AY Y-AY X SPX Y SPY X SPX,Y SPY NZ NB OVF NB Status Words/ Cycles 1/1 1/1 1/1 2/2* 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1
0100010000 0000000000 0011101000 0011011000 0001011100 0011011111 0001010100 0011010100 0000000001 0000000010 0000000011
Note: * The assembler automatically provides an operand for the second word of the LAW and LWA instruction.
Rev.5.00, Sep.11.2003, page 128 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 33
Operation Load A from memory
RAM Register Instructions
Mnemonic LAM LAMX LAMY LAMXY Operation Code 0010010000 0010010001 0010010010 0010010011 0110010000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001000000 0001000001 0001000010 0001000011 0010010100 0010010101 0010010110 0010010111 0110010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001010000 0001010001 0011010000 0011010001 Function MA MA X SPX MA Y SPY MA X SPX, Y SPY MA MB MB X SPX MB Y SPY MB X SPX, Y SPY AM AM X SPX AM Y SPY AM X SPX, Y SPY AM A M, Y + 1 Y A M, Y + 1 Y X SPX A M, Y - 1 Y A M, Y - 1 Y X SPX NB 1/1 NZ 2/2 1/1 1/1 2/2 1/1 Status Words/ Cycles 1/1
Load A from memory Load B from memory
LAMD d LBM LBMX LBMY LBMXY
Load memory from A
LMA LMAX LMAY LMAXY
Load memory from A Load memory from A, increment Y
LMAD d LMAIY LMAIYX LMADY LMADYX
Load memory from A, decrement Y
Rev.5.00, Sep.11.2003, page 129 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 33
Operation Exchange memory and A
RAM Register Instructions (cont)
Mnemonic XMA XMAX XMAY XMAXY Operation Code 0010000000 0010000001 0010000010 0010000011 0110000000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0011000000 0011000001 0011000010 0011000011 Function MA MA X SPX MA Y SPY MA X SPX, Y SPY MA MB MB X SPX MB Y SPY MB X SPX, Y SPY 2/2 1/1 Status Words/ Cycles 1/1
Exchange memory and A Exchange memory and B
XMAD d XMB XMBX XMBY XMBXY
Rev.5.00, Sep.11.2003, page 130 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 34
Operation Add immediate to A Increment B Decrement B Decimal adjust for addition Decimal adjust for subtraction Negate A Complement B Rotate right A with carry Rotate left A with carry Set carry Reset carry Test carry Add A to memory Add A to memory Add A to memory with carry Add A to memory with carry Subtract A from memory with carry Subtract A from memory with carry OR A and B AND memory with A AND memory with A OR memory with A OR memory with A EOR memory with A EOR memory with A
Arithmetic Instructions
Mnemonic AI i IB DB DAA DAS NEGA COMB ROTR ROTL SEC REC TC AM AMD d AMC AMCD d SMC SMCD d OR ANM ANMD d ORM ORMD d EORM EORMD d Operation Code 1 0 1 0 0 0 i3 i2 i1 i0 Function A+iA B+1B B-1B Status OVF NZ NB Words/ Cycles 1/1 1/1 1/1 1/1 1/1 A+1A BB 1/1 1/1 1/1 1/1 1 CA 0 CA CA M+AA M+AA M + A + CA A OVF CA M + A + CA A OVF CA M - A - CA A NB CA M - A - CA A NB CA ABA AMA AMA AMA AMA AMA AMA NZ NZ NZ NZ NZ NZ OVF OVF OVF OVF NB NB 1/1 1/1 1/1 1/1 2/2 1/1 2/2 1/1 2/2 1/1 1/1 2/2 1/1 2/2 1/1 2/2
0001001100 0011001111 0010100110 0010101010 0001100000 0101000000 0010100000 0010100001 0011101111 0011101100 0001101111 0000001000 0100001000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000011000 0100011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0010011000 0110011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0101000100 0010011100 0110011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000001100 0100001100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000011100 0100011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 35
Operation Immediate not equal to memory Immediate not equal to memory A not equal to memory A not equal to memory B not equal to memory Y not equal to immediate Immediate less than or equal to memory Immediate less than or equal to memory A less than or equal to memory A less than or equal to memory B less than or equal to memory A less than or equal to immediate
Compare Instructions
Mnemonic INEM i INEMD i,d ANEM ANEMD d BNEM YNEI i ILEM i ILEMD i,d ALEM ALEMD d BLEM ALEI i Operation Code 0 0 0 0 1 0 i3 i2 i1 i0 Function iM iM AM AM BM Yi iM iM AM AM BM Ai Status NZ NZ NZ NZ NZ NZ NB NB NB NB NB NB Words/ Cycles 1/1 2/2 1/1 2/2 1/1 1/1 1/1 2/2 1/1 2/2 1/1 1/1
0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000100 0100000100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001000100 0 0 0 1 1 1 i3 0 0 0 0 1 1 i3 i2 i2 i1 i0 i1 i0
0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000010100 0100010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0011000100 1 0 1 0 1 1 i3 i2 i1 i0
Table 36
Operation
Set memory bit Set memory bit
RAM Bit Manipulation Instructions
Mnemonic SEM n SEMD n,d REM n REMD n,d TM n TM n,d Operation Code 0 0 1 0 0 0 0 1 n1 n0 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 0 n1 n0 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 1 n1 n0 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Function i M (n) i M (n) 0 M (n) 0 M (n) M (n) M (n) Status Words/ Cycles 1/1 2/2 1/1 2/2 1/1 2/2
Reset memory bit Reset memory bit Test memory bit Test memory bit
Rev.5.00, Sep.11.2003, page 132 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 37
Operation Branch on status 1 Long branch on status 1 Long jump unconditionally Subroutine jump on status 1 Long subroutine jump on status 1 Table branch Return from subroutine Return from interrupt
ROM Address Instructions
Mnemonic BR b BRL u JMPL u CAL a CALL u TBR p RTN RTNI Operation Code 1 1 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 a5 a4 a3 a2 a1 a0 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 1 p3 p2 p1 p0 0000010000 0000010001 1 IE, carry restored ST 1 1 Function Status 1 1 Words/ Cycles 1/1 2/2 2/2 1/2 2/2 1/1 1/3 1/3
Table 38
Operation
Input/Output Instructions
Mnemonic SED SEDD m RED REDD m TD TDD m LAR m LBR m LRA m LRB m Pp Operation Code 0011100100 1 0 1 1 1 0 m3 m2 m1 m0 0001100100 1 0 0 1 1 0 m3 m2 m1 m0 0011100000 1 0 1 0 1 0 m3 m2 m1 m0 1 0 0 1 0 1 m3 m2 m1 m0 1 0 0 1 0 0 m3 m2 m1 m0 1 0 1 1 0 1 m3 m2 m1 m0 1 0 1 1 0 0 m3 m2 m1 m0 0 1 1 0 1 1 p3 p2 p1 p0 R (m) A R (m) B A R (m) B R (m) Function 1 D (Y) 1 D (m) 0 D (Y) 0 D (m) D (Y) D (m) Status Words/ Cycles 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/2
Set discrete I/O latch Set discrete I/O latch direct Reset discrete I/O latch Reset discrete I/O latch direct Test discrete I/O latch Test discrete I/O latch direct Load A from R-port register Load B from R-port register Load R-port register from A Load R-port register from B Pattern generation
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 39
Operation No operation Start serial Standby mode/watch mode* Stop mode/watch mode
Control Instructions
Mnemonic NOP STS SBY STOP Operation Code 0000000000 0101001000 0101001100 0101001101 Function Status Words/ Cycles 1/1 1/1 1/1 1/1
Note: * Only after a transition from subactive mode.
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HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 40
R8 R9 H L 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F One word/two cycle instructions One word/three cycle instructions
TD LWI i(2) LBI i(4) LYI i(4) LXI i(4) LAI i(4) LBR m(4) LAR m(4) REDD m(4) LAMR m(4) AI i(4) LMIIY i(4) TDD m(4) ALEI i(4) LRB m(4) LRA m(4) SEDD m(4) XMRA m(4) XMB(XY) LMADY(X) BLEM SYY SED XMA(XY) LAM(XY) ROTR ROTL SEM n(2) LMA(XY) DAA TBR p(4) LBA LYA LXA REC DB DY SEC SMC DAS NEGA LBM(XY) LMAIY(X) BNEM AYY RED
Opcode Map
0 0 1
RTNI
2
3
4
ALEM
5
6
7
8
AM AMC
9
A
B
C
ORM EORM
D
E
F
NOP RTN
XSPX XSPY XSPXY ANEM
INEM i(4) ILEM i(4) LAB LASPY LASPX YNEI i(4) REM n(2) ANM LAY TM n(2) IB IY TC
RAM direct address instructions (two word/two cycle)
Two word/two cycle instructions
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Absolute Maximum Ratings
Item Power supply voltage Programming voltage Pin voltage Allowable input current (total) Allowable output current (total) Allowable input current (per pin) Symbol VCC VPP VT l0 - l0 l0 -l0 Topr Value -0.3 to +7.0 -0.3 to +14.0 -0.3 to VCC+0.3 100 50 4 30 Allowable output current (per pin) 4 20 Operating temperature -20 to +75 -40 to +85 Storage temperature Tstg -55 to +125 Unit V V V mA mA mA mA mA mA C C C 2 3 4,5 4,6 7,8 7,9 10, 12 11, 12 13 1 Notes
Notes: Permanent damage may occur if these maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to the HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, and HD407C4389 TEST (VPP) pin. 2. The allowable input current (total) is the sum of all currents flowing from I/O pins to ground at the same time. 3. The allowable output current (total) is the sum of all currents flowing from VCC to I/O pins. 4. The allowable input current (per pin) is the maximum current allowed to flow from any one I/O pin to ground. 5. Applies to pins D0 to D3, D8, D9 and port R. 6. Applies to pins D4 to D7. 7. The allowable output current (per pin) is the maximum current allowed to flow from VCC to any one I/O pin. 8. Applies to pins D4 to D9 and port R. 9. Applies to pins D0 to D3. 10. Applies to Mask ROM TM 11. Applies to ZTAT . 12. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage Vcc shown in the electrical characteristics tables can be applied). 13. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details.
Rev.5.00, Sep.11.2003, page 136 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Electrical Characteristics
DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084, HD40A4084, HD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404082, HCD40C4082, HCD404084, HCD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = - 40C to +85C, unless otherwise specified)
Item Symbol Pins min. typ. max. -- Unit Test conditions Notes
Input high voltage VIH
RESET,SCK, 0.90VCC SI, INT0, WU0, EVNB OSC1 VCC-0.3 RESET,SCK, -0.3 SI, INT0, WU0, EVNB OSC1 -0.3 SCK,SO, TOB, VCC-0.5 TOC SCK,SO, TOB, -- TOC RESET,SCK, SI,INT0, WU0, EVNB, OSC1, TOB, TOC, SO VCC --
VCC+0.3 V
-- --
VCC+0.3 V 0.10VCC V
External clock operation
Input low voltage
VIL
-- -- -- --
0.3 -- 0.4 1
V V V A
External clock operation -IOH=0.3mA IOL=0.4mA Vin=0V to VCC 1
Output high voltage
VOH
Output low voltage VOL I/O leakage current | IIL|
Active mode lCC1 current dissipation lCC2 lCC3 Standby mode current dissipation lSBY2 lSBY3 Subactive mode lSUB current dissipation Watch mode lWTC current dissipation lSBY1
-- -- -- -- -- --
1.5 3.5 1.2 2.5 0.4 1.0 0.3 0.7 2.7 9.0 2.2 4.5 1.0 1.5 0.6 1.3 0.3 0.6 0.2 0.5 1.4 4.0 1.0 2.5 18 6 35 10
mA mA mA mA mA mA mA mA mA mA mA mA A A
VCC=5V, fOSC=4MHz VCC=3V, fOSC=800kHz VCC=5V, fOSC=8MHz VCC=5V, fOSC=4MHz VCC=3V, fOSC=800kHz VCC=5V, fOSC=8MHz VCC = 3V, 32 kHz oscillator used VCC = 3 V, 32 kHz oscillator used
2, 7 2, 8 2, 7 2, 8 2, 9 2, 10 3, 7 3, 8 3, 7 3, 8 3, 9 3, 10 4, 5 4, 5
VCC
-- -- -- -- -- --
VCC VCC
-- --
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Item Symbol Pins VCC VCC min. -- 1.5 typ. max. -- -- 5 -- Unit A V Test conditions VCC = 3 V, no 32 kHz oscillator no 32 kHz oscillator Notes 4 6
Stop mode current lSTOP dissipation Stop mode retention voltage VSTOP
Notes: 1. Excludes output buffer current. 2. Power supply current when the MCU is in the reset state and there are no I/O currents. Test Conditions MCU State Pin States * Reset state * RESET, TEST: At ground
3. Power supply current when the on-chip timers are operating and there are no I/O currents. Test Conditions MCU State * I/O: Same as reset state * Standby mode * fcyc = fOSC/4 Pin States * RESET: At VCC * TEST: At ground * D port, R port: At VCC 4. Power supply current when there are no I/O currents. Test Conditions Pin States * RESET: At VCC * TEST: At ground * D port, R port: At VCC 5. 6. 7. 8. 9. Applies to HD404374 Series. Voltage needed to retain RAM data. Applies to HD404374, HD404384, and HD404389 Series. Applies to HD404082 and HD404084 Series. Applies to HD40A4374/2, HD407A4374, HD40A4384/2, HD407A4384, HD40A4389/8 and HD407A4389. 10. Applies to HD40A4082/1 and HD40A4084.
Rev.5.00, Sep.11.2003, page 138 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series I/O Characteristics for Standard Pins DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084, HD40A4084, HD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404082, HCD40C4082, HCD404084, HCD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = -40C to +85C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current MOS pull-up current Symbol VIH VIL VOH VOL | IIL | -IPU Pins R port, D8, D9 R port, D8, D9 R port, D8, D9 R port, D8, D9 R port, D8, D9 R port, D8, D9 min. 0.7VCC -0.3 VCC-0.5 -- -- 10 typ. max. -- -- -- -- -- 50 VCC+0.3 0.3VCC -- 0.4 1 150 Unit V V V V A A -IOH=0.3mA IOL=0.4mA Vin=0V to VCC VCC=3V, Vin=0V 1 Test conditions Notes
Note:
1. Excludes output buffer current.
I/O Characteristics for High-Current Pins DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084, HD40A4084, HD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404082, HCD40C4082, HCD404084, HCD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = -40C to +85C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Symbol VIH VIL VOH Pins D0 to D7 D0 to D7 D4 to D7 D0 to D3 Output low voltage VOL D0 to D3 D4 to D7 I/O leakage current MOS pull-up current | IIL | -IPU D0 to D7 D0 to D7 min. 0.7VCC -0.3 VCC-0.5 VCC-2.0 -- -- -- 10 typ. max. -- -- -- -- -- -- -- 50 VCC+0.3 0.3VCC -- -- 0.4 2.0 1 150 Unit V V V V V V A A -IOH=0.3mA -IOH=10mA, VCC=4.5 to 5.5V IOL=0.4mA IOL=15mA VCC=4.5V to 5.5V Vin =0V to VCC VCC=3V, Vin=0V 1 Test conditions Notes
Note:
1. Excludes output buffer current.
Rev.5.00, Sep.11.2003, page 139 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series A/D Converter Characteristics (HD404374/HD404384/HD404389 Series) (Mask ROM: VCC = 1.8 V to TM 5.5 V, GND = 0 V, Ta = -20C to +75C; ZTAT : VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Analog power supply voltage Analog input voltage AVCC-AVSS current Analog input capacitance Resolution Number of inputs Absolute accuracy Symbol AVCC AVin IAD CAin AN0 to AN5 Pins AVCC AN0 to AN5 min. VCC-0.3 AVSS -- -- -- 0 -- typ. max. VCC -- -- 15 10 -- -- VCC+0.3 AVCC 500 -- -- 4 4.0 Unit V V A pF bit channel LSB VCC=AVCC=1.8V to 5.5V 2 VCC=AVCC=2.0V to 5.5V 3 Conversion time 125 65 Input impedance AN0 to AN5 1 -- -- -- -- -- -- tcyc tcyc M* VCC=AVCC=1.8V to 2.0V 2 or less VCC=AVCC=2.0V to 5.5V VCC=AVCC=5.0V Test conditions Notes 1
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting range is 1.8 V TM AVCC5.5V (Mask ROM), 2.0V AVCC 5.5V (ZTAT ). 2. Applies to Mask ROM. TM 3. Applies to ZTAT .
Rev.5.00, Sep.11.2003, page 140 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series AC Characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084, HD40A4084, HD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404082, HCD40C4082, HCD404084, HCD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = -40C to +85C, unless otherwise specified)
Item Clock oscillation frequency (ceramic oscillator, crystal oscillator) Clock oscillation frequency (Resistance oscillation) Instruction cycle time (external clock, ceramic oscillator, crystal oscillator) tcyc 0.89 0.47 tsubcyc -- -- Instruction cycle time tcyc (Resistance oscillation) Oscillation settling time tRC (external clock input) Oscillation settling time tRC (ceramic oscillator) Oscillation settling time(crystal oscillator) tRC OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 X1,X2 OSC1, OSC2 OSC1 1.14 -- -- -- -- -- 105 52.5 tCPL OSC1 105 52.5 OSC1 -- -- 20 10 External clock fall time tCPf INT0, EVNB, WU0, high-level width OSC1 INT0, EVNB, WU0 -- -- 20 10 tIH 2 -- -- tcyc/tsubcyc ns ns -- -- ns -- -- 10 10 s s s ms ms ms s ms ns VCC=2.0 to 5.5V VCC=2.0 to 5.5V Ta=-10 to +60C, VCC=2.0 to 5.5V Rf=20 k VCC=2.0 to 5.5V fOSC=4MHz fOSC=8MHz fOSC=4MHz fOSC=8MHz fOSC=4MHz fOSC=8MHz fOSC=4MHz fOSC=8MHz s Division by 4 3 32 kHz oscillator used, 4 division by 8 32 kHz oscillator used, 4 division by 4 Division by 4 Rf=20 k 5 6 6 6 4, 6 5, 6 7 3, 7 7 3, 7 7 3, 7 7 3, 7 8 Symbol fOSC Pins OSC1, OSC2 min. 0.4 0.4 fx fOSC X1,X2 OSC1, OSC2 -- 0.5 0.5 typ. -- -- max. 4.5 8.5 kHz MHz Division by 4 Rf=20 k Unit MHz Test conditions Division by 4 Notes 1 1, 3 4 2, 13 2, 12
32.768 -- 2.0 2.2 3.5 3.5
244.14 -- 122.07 -- -- -- -- -- -- -- -- 8.0 7.5 7.5 30 2 0.5 --
Oscillation setting time tRC (Resistance oscillation) External clock highlevel width External clock lowlevel width tCPH
External clock rise time tCPr
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HD404374/HD404384/HD404389/HD404082/HD404084 Series
Item INT0, EVNB, WU0, low-level width RESET rise time Input capacitance Symbol tIL Pins INT0, EVNB, WU0 RESET RESET All input pins except TEST TEST TEST Capacitance between CRF OSC1 and OSC2 (Resistance oscillation) OSC1, OSC2 min. 2 2 -- -- -- -- -- typ. -- -- -- -- -- -- -- max. -- -- 20 15 15 40 1 Unit tcyc/tsubcyc tcyc ms pF pF pF pF f=1MHz,Vin=0V 10 11 5 Test conditions Notes 8 9 9
RESET low-level width tRSTL tRSTr Cin
Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range 0.4 MHzfOSC1.0 MHz or 1.6 MHzfOSC8.5 MHz. The SSR1 bit of the system clock select register (SSR) should be set to 0 and 1, respectively. 2. The typ. value is the value when VCC = 3.5 V. 3. Applies to HD40A4372/4, HD40A4382/4, HD40A4388/9, HD40A4081/2, HD40A4084, HD407A4374, HD407A4384 and HD407A4389 when VCC = 4.0 to 5.5 V. 4. Applies to HD404374 Series. 5. Applies to HD40C4372/4, HD407C4374, HD40C4382/4, HD407C4384, HD40C4388/9, HD407C4389, HD40C4081/2, HCD40C4082, HD40C4084, HCD40C4084. 6. The oscillation settling time is defined as follows: (1) The time required for the oscillation to settle after VCC has reached standard minimum at power-on. (2) The time required for the oscillation to settle after RESET input has gone low when stop mode is cleared. To ensure enough time for the oscillation to settle at power-on hold the RESET input low for at least time tRC. The oscillation settling time will depend on the circuit constants and stray capacitance. The resonator should be determined in consultation with the resonator manufacturer. With regard to the system clock (OSC1, OSC2), bits MIS1 and MIS0 in the miscellaneous register (MIS) should be set according to the oscillation settling time of the resonator used. 7. See figure 79. 8. See figure 80. 9. See figure 81. 10. Applies to Mask ROM. TM 11. Applies to ZTAT . 12. Applies to HD40C4081/2, HCD40C4082, HD40C4084, HCD40C4084. 13. Applies to HD40C4372/4, HD407C4374, HD40C4382/4, HD407C4384, HD40C4388/9, HD407C4389.
Rev.5.00, Sep.11.2003, page 142 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial interface timing characteristics DC Characteristics (HD404372, HD40A4372, HD40C4372, HD404374, HD40A4374, HD40C4374, HD404382, HD40A4382, HD40C4382, HD404384, HD40A4384, HD40C4384, HD404388, HD40A4388, HD40C4388, HD404389, HD40A4389, HD40C4389, HD404081, HD40A4081, HD40C4081, HD404082, HD40A4082, HD40C4082, HD404084, HD40A4084, HD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = -20C to +75C; HCD404082, HCD40C4082, HCD404084, HCD40C4084: VCC = 1.8 V to 5.5 V, GND = 0 V, Ta = +75C; HD407A4374, HD407C4374, HD407A4384, HD407C4384, HD407A4389, HD407C4389: VCC = 2.0 V to 5.5 V, GND = 0 V, Ta = -40C to +85C, unless otherwise specified)
Item Serial clock cycle time Serial clock high-level width Serial clock low-level width Serial clock rise time Serial clock fall time Serial output data delay time Symbol tScyc tSCKH tSCKL tSC Kr tSCKf tDSO Pins SCK SCK SCK SCK SCK SO SI SI min. 1 0.4 0.4 -- -- -- 200 200 typ. max. -- -- -- -- -- -- -- -- -- -- -- 100 100 300 -- -- Unit tcyc tScyc tScyc ns ns ns ns ns Test conditions See load in figure 83 See load in figure 83 See load in figure 83 See load in figure 83 See load in figure 83 See load in figure 83 Notes 1 1 1 1 1 1 1 1
Serial input data setup tSSI time Serial input data hold time tHSI
During Serial Clock Input
Item Serial clock cycle time Serial clock high-level width Serial clock low-level width Serial clock rise time Serial clock fall time Serial output data delay time Symbol tScyc tSCKH tSCKL tSC Kr tSCKf tDSO Pins SCK SCK SCK SCK SCK SO SI SI min. 1 0.4 0.4 -- -- -- 200 200 typ. max. -- -- -- -- -- -- -- -- -- -- -- 100 100 300 -- -- Unit tcyc tScyc tScyc ns ns ns ns ns See load in figure 83 Test conditions Notes 1 1 1 1 1 1 1 1
Serial input data setup tSSI time Serial input data hold time tHSI
Note:
1. See figure 82.
Rev.5.00, Sep.11.2003, page 143 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
OSC1
1/fCP VCC-0.3V 0.3V tCPr tCPH tCPf
tCPL
Figure 79 External Clock Input Waveform
0
,EVNB,
0
0.9VCC 0.1VCC
tIH
tIL
Figure 80 Interrupt Timing
0.9VCC 0.1VCC
tRSTL
tRSTr
Figure 81 Reset Timing
Rev.5.00, Sep.11.2003, page 144 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
tScyc tSCKf VCC-0.5V(0.9VCC)* 0.4V(0.1VCC)* tDSO tSCKr tSCKL tSCKH
SO
VCC-0.5V 0.4V tSSI tHSI
SI
0.9VCC 0.1VCC
Note : VCC-0.5V and 0.4V are the voltages during serial clock output. 0.9 VCC and 0.1 VCC are the voltages during serial clock input.
Figure 82 Serial Interface Timing
VCC RL=2.6k1/2 Test point C=30pF R=12k1/2 1S2074(H) or equivalent
Figure 83 Timing Load Circuit
Rev.5.00, Sep.11.2003, page 145 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
5.0 2.5
Ta=25C fcyc=fosc/4 typ
4.0 fosc=8MHz
ICC (mA)
Ta=25C Rf=20k
2.0
fcyc=fosc/4 typ
ICC (mA)
3.0
1.5
2.0 fosc=4MHz 1.0 fosc=2MHz fosc=800kHz fosc=400kHz 1 2 3 VCC (V) 4 5 6
1.0
0.5
0.0
0.0 1 2 3 VCC (V) 4 5 6
(a) ICC vs. VCC characteristic (ceramic oscillation, crystal oscillation)
2.5
(b) ICC vs. VCC characteristic (resistance oscillation)
5.0
Ta=25C Rf=20k
typ
4.0
Ta=25C typ
fosc (MHz)
fosc (MHz)
2.0
3.0
2.0 VCC=5V VCC=3.5V VCC=2V
1.5 1.0
1.0 1 2 3 VCC (V) 4 5 6
0.0 0 10 20 30 Rf (k ) 40 50
(c) fOSC vs. VCC characteristic (resistance oscillation)
2.5
(d) fOSC vs. Rf characteristic (resistance oscillation)
5.0
Ta=25C typ
2.0
VCC-VOH (V)
Ta=25C typ
4.0 VCC=4.5V
VOL (V)
1.5
VCC=5V VCC=5.5V
3.0 VCC=4.5V 2.0 VCC=5V VCC=5.5V
1.0
0.5
1.0
0.0 0 10 20 30 IOL (mA) 40 50
0.0 0 5 10 15 -IOH (mA) 20 25
(e) VOL vs. IOL characteristic (pins D4 to D7)
(f) VCC - VOH vs. IOH characteristic (pins D0 to D3)
Figure 84 HD404374, HD404384, and HD404389 Series Characteristic Curves (Reference Values)
Rev.5.00, Sep.11.2003, page 146 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
2.5 2.5
Ta=25C fcyc=fosc/4 typ
2.0
fosc=8MHz 2.0 fosc=4MHz
ICC (mA)
Ta=25C Rf=20k fcyc=fosc/4 typ
ICC (mA)
1.5
1.5
1.0
fosc=2MHz fosc=800kHz fosc=400kHz
1.0
0.5
0.5
0.0 1 2 3 VCC (V) 4 5 6
0.0 1 2 3 4 VCC (V) 5 6
(a) ICC vs. VCC characteristic (ceramic oscillation, crystal oscillation)
2.5
(b) ICC vs. VCC characteristic (resistance oscillation)
5.0
Ta=25C typ
4.0 2.0
fosc (MHz) fosc (MHz)
3.0
2.0 VCC=5V VCC=3.5V VCC=2V
1.5
Ta=25C Rf=20k typ
1.0
1.0 1 2 3 4 VCC (V) 5 6
0.0 0 10 20 30 Rf (k) 40 50
(c) fOSC vs. VCC characteristic (resistance oscillation)
(d) fOSC vs. Rf characteristic (resistance oscillation)
2.5
5.0
Ta=25C typ
2.0 VCC=4.5V 1.5 VCC=5V VCC=5.5V
VCC-VOH (V)
Ta=25C typ
4.0
VOL (V)
3.0 VCC=4.5V 2.0 VCC=5V VCC=5.5V
1.0
0.5
1.0
0.0 0 10 20 30 40 50 IOL (mA)
0.0 0 5 10 15 20 25 -IOH (mA)
(e) VOL vs. IOL characteristic (pins D4 to D7)
(f) VCC - VOH vs. IOH characteristic (pins D0 to D3)
Figure 85 HD404082 and HD404084 Series Characteristic Curves (Reference Values)
Rev.5.00, Sep.11.2003, page 147 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Package Dimensions
11.0 11.2 Max
Unit: mm
16
8.0
30
1 0.65
*0.32 0.08 0.30 0.06
15
0.10 M
2.00 Max
*0.17 0.05 0.15 0.04
10.0 0.2
1.05 Max
1.0 0 - 8
0.5 0.1
0.10
0.10 0.10
*Dimension including the plating thickness Base material dimension
Package Code JEDEC EIAJ Weight (reference value)
FP-30D -- -- --
Rev.5.00, Sep.11.2003, page 148 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Unit: mm
27.1 27.9 Max 28 15
10.8 Max
1
1.0
2.41 Max
14
5.10 Max
8.8
10.16
0.51 Min
2.54 Min
1.78 0.25
0.48 0.10
0.25 - 0.05 0 - 15
Package Code JEDEC EIAJ Weight (reference value)
+ 0.11
DP-28S -- Conforms 1.9 g
Unit: mm 9.0 0.2 7 36 25
9.0 0.2
37
24
48 12
13
*0.17 0.05
0.15 0.04
1.70 Max
1 *0.22 0.05 0.20 0.04
0.08
M
0.5
1.0 0.75 0 - 8 0.5 0.1
0.08
0.10 0.07
1.40
*Dimension including the plating thickness Base material dimension
Package Code JEDEC EIAJ Weight (reference value)
FP-48B -- -- 0.2 g
Rev.5.00, Sep.11.2003, page 149 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Note on ROM Ordering
Please note the following when ordering HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382 and HD40C4382 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 4-kwords version (HD404374, HD40A4374, HD40C4372, HD404384, HD40A4384, HD40C4384). The program that converts ROM data to mask drawing data is the same as that used for the 4-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission.
2-kword ROM version: HD404372, HD40A4372, HD40C4372, HD404382, HD40A4382, HD40C4382 Write all-1 data to addresses $0800 to $0FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words)
$003F $0040
Program and pattern area (2,048 words)
$07FF $0800
Not used*
$0FFF Note: * Write all-1 data in not used area.
Rev.5.00, Sep.11.2003, page 150 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Please note the following when ordering HD404388, HD40A4388 and HD40C4388 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 16-kwords version (HD404389, HD40A4389, HD40C4389). The program that converts ROM data to mask drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission.
8-kword ROM version: HD404388, HD40A4388, HD40C4388 Write all-1 data to addresses $2000 to $3FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words)
$003F $0040
Program and pattern area (8,192 words)
$1FFF $2000
Not used*
$3FFF Note: * Write all-1 data in not used area.
Rev.5.00, Sep.11.2003, page 151 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series Please note the following when ordering HD404081, HD40A4081 and HD40C4081 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 2-kwords version (HD404082, HD40A4082, HD40C4082). The program that converts ROM data to mask drawing data is the same as that used for the 2-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission.
1-kword ROM version: HD404081, HD40A081, HD40C4081 Write all-1 data to addresses $0400 to $07FF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words)
$003F $0040
Program and pattern area (1,024 words)
$03FF $0400
Not used*
$07FF Note: * Write all-1 data in not used area.
Rev.5.00, Sep.11.2003, page 152 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Option List
HD404372, HD404374, HD40A4372, HD40A4374, HD40C4372, HD40C4374
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Renesas Technology entry) Year Month Day
1. ROM Size
Standard operation version: HD404372 High-speed operation version: HD40A4372 CR oscillation version: HD40C4372 Standard operation version: HD404374 High-speed operation version: HD40A4374 CR oscillation version: HD40C4374 4 kwords 2 kwords
2. Function Options
* * 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, no realtime clock time base
Note: * When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2).
3. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
* * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
Rev.5.00, Sep.11.2003, page 153 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series 4. System Oscillator (OSC1-OSC2) (Shading means selection is not available)
HD404372/4, HD40A4372/4 Ceramic oscillator Crystal oscillator External clock Resistance oscillator f= f= f= MHz MHz MHz HD40C4372/4
5. Subsystem Oscillator (X1 X2)
Not used Crystal resonator -- f = 32.768 kHz
6. Stop Mode
Yes (used) No (not used)
7. Package
FP-30D FP-48B*
Note: *The WS version will become available at the beginning of mass production.
Rev.5.00, Sep.11.2003, page 154 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Option List
HD404382, HD404384, HD40A4382, HD40A4384, HD40C4382, HD40C4384
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Renesas Technology entry) Year Month Day
1. ROM Size
Standard operation version: HD404382 High-speed operation version: HD40A4382 CR oscillation version: HD40C4382 Standard operation version: HD404384 High-speed operation version: HD40A4384 CR oscillation version: HD40C4384 4 kwords 2 kwords
2. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
* * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
3. System Oscillator (OSC1-OSC2) (Shading means selection is not available)
HD404382/4, HD40A4382/4 Crystal oscillator Ceramic oscillator External clock Resistance oscillator f= f= f= MHz MHz MHz f= MHz HD40C4382/4
Rev.5.00, Sep.11.2003, page 155 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series 4. Stop Mode
Yes (used) No (not used)
5. Package
FP-30D DP-28S FP-48B*
Note: * The WS version will become available at the beginning of mass production.
Rev.5.00, Sep.11.2003, page 156 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Option List
HD404388, HD404389, HD40A4388, HD40A4389, HD40C4388, HD40C4389
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Renesas Technology entry) Year Month Day
1. ROM Size
Standard operation version: HD404388 High-speed operation version: HD40A4388 CR oscillation version: HD40C4388 Standard operation version: HD404389 High-speed operation version: HD40A4389 CR oscillation version: HD40C4389 16 kwords 8 kwords
2. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
* * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
3. System Oscillator (OSC1-OSC2) (Shading means selection is not available)
HD404388/9, HD40A4388/9 Crystal oscillator Ceramic oscillator External clock Resistance oscillator f= f= f= MHz MHz MHz f= MHz HD40C4388/9
Rev.5.00, Sep.11.2003, page 157 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series 4. Stop Mode
Yes (used) No (not used)
5. Package
FP-30D
Rev.5.00, Sep.11.2003, page 158 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Option List
HD404081, HD404082, HCD404082, HD40A4081, HD40A4082, HD40C4081, HD40C4082, HCD40C4082
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Renesas Technology entry) Year Month Day
1. ROM Size
Standard operation version: HD404081 High-speed operation version: HD40A4081 CR oscillation version: HD40C4081 Standard operation version: HD404082 Standard operation version: HCD404082 High-speed operation version: HD40A4082 CR oscillation version: HD40C4082 CR oscillation version: HCD40C4082 2 kwords 1 kwords
2. System Oscillator (OSC1-OSC2) (Shading means selection is not available)
HD404081/2, HD40A4081/2, HCD404082 Crystal oscillator Ceramic oscillator External clock Resistance oscillator f= f= f= MHz MHz MHz f= MHz
HD40C4081/2, HCD40C4082
3. Stop Mode
Yes (used) No (not used)
4. Package
FP-30D DP-28S Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
Rev.5.00, Sep.11.2003, page 159 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Option List
HD404084, HCD404084, HD40A4084, HD40C4084, HCD40C4084
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Renesas Technology entry) Year Month Day
1. ROM Size
Standard operation version: HD404084 Standard operation version: HCD404084 High-speed operation version: HD40A4084 CR oscillation version: HD40C4084 CR oscillation version: HCD40C4084 4 kwords
2. System Oscillator (OSC1-OSC2) (Shading means selection is not available)
HD404084, HD40A4084, HCD404084 HD40C4084, HCD40C4084 Crystal oscillator Ceramic oscillator External clock Resistance oscillator f= f= f= MHz MHz MHz
3. Stop Mode
Yes (used) No (not used)
4. Package
FP-30D DP-28S Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
Rev.5.00, Sep.11.2003, page 160 of 161
HD404374/HD404384/HD404389/HD404082/HD404084 Series
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
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Rev.5.00, Sep.11.2003, page 161 of 161

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